[Intel-gfx] [PATCH] drm/i915: fix relaxed tiling on gen2

[Chris Wilson]

On Sat, 26 Mar 2011 15:22:57 +0100, Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> A tile on gen2 has a size of 2kb, stride of 128 bytes and 16 rows.

You know thats what it says in the gen2 docs as well under FENCE. :(
 
> Userspace was broken and assumed 8 rows. Complain with a printk_once
> and disallow such tiling requests.

However, we know that userspace only requests correctly aligned regions by
accident due to the rounding up to the next bucket size in libdrm.

> Also experiments and randoms cues from i81x docs suggest that y-tiling
> doesn't work with fences (it's already known to be broken on the blitter).
> Original idea seems to be to use y-tiling for textures with a manually
> tiling upload path. Hence also disallow y-tiling - current userspace
> doesn't use it at all, anyway.

gen2 docs say that the FENCE upload via the CPU can handle Y-tiling on
all chipsets but 855GM. Go figure. (To handle Y-tiling uploads on 855GM it
says to BLT from X to Y...)

In which case it is only an error in i915_gem_fault() for 855GM &
Y-tiling.

So whilst I think we've found the right bug, I don't quite think we've got
the right patch yet.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre