[Intel-gfx] [PATCH] drm/i915: fix relaxed tiling on gen2 v2

[Chris Wilson]

On Sat, 26 Mar 2011 20:55:15 +0100, Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> A tile on gen2 has a size of 2kb, stride of 128 bytes and 16 rows.

Nice patch, marries the code to the documentation (afaict). Should split
it into its two distinct fixes though. Both -next material, perhaps. And
thankfully explains the 2*8 fixup we needed for userspace, but note it is
also wrong for Y-tiling on gen2.

So, afaics, there is no way with the current interface the kernel can stop
userspace from shooting itself in the foot.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre