[Intel-gfx] [PATCH 4/6] drm/i915: Add an interface to dynamically change the cache level

[Chris Wilson]

On Wed, 30 Mar 2011 09:59:55 -0700, Eric Anholt <eric at anholt.net> wrote:
> On Wed, 30 Mar 2011 08:09:47 +0100, Chris Wilson <chris at chris-wilson.co.uk> wrote:
> > The series looks really good, only one quibble below.
> > 
> > On Tue, 29 Mar 2011 16:59:53 -0700, Eric Anholt <eric at anholt.net> wrote:
> > > +int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
> > > +				    enum i915_cache_level cache_level)
> > > +	if (cache_level == I915_CACHE_NONE) {
> > > +		/* If we're coming frm LLC cached, then we haven't
> > > +		 * actually been tracking whether the data is in the
> > > +		 * CPU cache or not, since we only allow one bit set
> > > +		 * in obj->write_domain.  Just set it to the CPU cache
> > > +		 * for now.
> > > +		 */
> > > +		BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
> > > +		obj->base.write_domain = I915_GEM_DOMAIN_CPU;
> > > +	}
> > 
> > [We can rearrange the code to convert the BUG_ON into a
> >  if (WARN_ON()) return -EBUSY;.]
> > 
> > I think this is overkill, at least by my interpretation of the old BLT
> > docs which imply that cache line invalidation (both CPU and GPU) is done
> > for snooped PTEs on MI_FLUSH.
> 
> And what about a CPU write through the GTT?

Even on SNB these are still UC. And we should try hard not to, as the
specs give dire warnings about writing to snooped PTEs through the GTT.
(Since we will bypass the caches with the write, aiui, and cause
confusion.)

> Or the CPU writes to the
> pages before we turned them into a BO and cleared their CPU write domain
> flag without actually clflushing them?

That's a valid argument. Just frustrated by the necessity.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre