[Intel-gfx] [PATCH] drm/i915: Reset GMBUS controller after NAK

[Chris Wilson]

On Thu, 31 Mar 2011 16:16:27 +0100, Steven Newbury <steve at snewbury.org.uk> wrote:
> ----- Original message -----
> > On Wed, 30 Mar 2011 17:07:11 +0100
> > Chris Wilson <chris at chris-wilson.co.uk> wrote:
> > 
> > > Once a NAK has been asserted by the slave, we need to reset the GMBUS
> > > controller in order to continue. This is done by asserting the Software
> > > Clear Interrupt bit and then clearing it again to restore operations.
> > > 
> > > If we don't clear the NAK, then all future GMBUS xfers will fail,
> > > including DDC probes and EDID retrieval.
> > > 
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35781
> > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> > > ---
> > 
> > This one fixes the issue I was seeing on my HP test machine; LVDS DDC
> > probing seems to work ok once this fix is applied.
> > 
> > -- 
> Could this be related to my inability to successfully probe the ch7036 with the ChromeOS Chrontel driver? Is it worth me testing it again with this patch applied? (I'm currently waiting to hear back from Zotac, my board supplier)

Hmm. Depends, but unlikely. I would have thought the nm10_gpio driver
you were using used it's only bitbanging on the GPIO lines rather than
GMBUS. If in doubt, disable the use of GMBUS by 

diff --git a/drivers/gpu/drm/i915/intel_i2c.c
b/drivers/gpu/drm/i915/intel_i2c.c
index d3b903b..ef9f664 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -401,7 +401,7 @@ int intel_setup_gmbus(struct drm_device *dev)
                bus->reg0 = i | GMBUS_RATE_100KHZ;
 
                /* XXX force bit banging until GMBUS is fully debugged */
-               if (IS_GEN2(dev))
+               if (1)
                        bus->force_bit = intel_gpio_create(dev_priv, i);
        }

-- 
Chris Wilson, Intel Open Source Technology Centre