[Intel-gfx] [PATCH] drm/i915: clarify IS_GEN vs IS_<product> usage
Jesse Barnes
jbarnes at virtuousgeek.org
Fri May 6 00:16:45 CEST 2011
We generally use the gen number to indicate the generation of the render
portion of the chip. In some cases this isn't the same as the display
generation (as in the case of G33 and GMA500). So codify the de facto
usage by converting some IS_GEN checks into product specific checks for
display related differences. (Note this makes me wonder about our G33
watermark handling; shouldn't it be like 965 not 945? I don't have one
to test with...).
Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_drv.c | 8 ++++-
drivers/gpu/drm/i915/i915_drv.h | 7 +++++
drivers/gpu/drm/i915/intel_display.c | 48 +++++++++++++++++-----------------
drivers/gpu/drm/i915/intel_dp.c | 8 +++---
4 files changed, 41 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 84bacc2..da040d7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -85,22 +85,26 @@ extern int intel_agp_enabled;
static const struct intel_device_info intel_i830_info = {
.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
+ .is_i8xx = 1,
};
static const struct intel_device_info intel_845g_info = {
.gen = 2,
.has_overlay = 1, .overlay_needs_physical = 1,
+ .is_i8xx = 1,
};
static const struct intel_device_info intel_i85x_info = {
.gen = 2, .is_i85x = 1, .is_mobile = 1,
.cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
+ .is_i8xx = 1,
};
static const struct intel_device_info intel_i865g_info = {
.gen = 2,
.has_overlay = 1, .overlay_needs_physical = 1,
+ .is_i8xx = 1,
};
static const struct intel_device_info intel_i915g_info = {
@@ -177,14 +181,14 @@ static const struct intel_device_info intel_ironlake_m_info = {
};
static const struct intel_device_info intel_sandybridge_d_info = {
- .gen = 6,
+ .gen = 6, .is_sandybridge = 1,
.need_gfx_hws = 1, .has_hotplug = 1,
.has_bsd_ring = 1,
.has_blt_ring = 1,
};
static const struct intel_device_info intel_sandybridge_m_info = {
- .gen = 6, .is_mobile = 1,
+ .gen = 6, .is_mobile = 1, .is_sandybridge = 1,
.need_gfx_hws = 1, .has_hotplug = 1,
.has_fbc = 1,
.has_bsd_ring = 1,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 196af79..2e185a9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -221,6 +221,7 @@ struct intel_device_info {
u8 gen;
u8 is_mobile : 1;
u8 is_i85x : 1;
+ u8 is_i8xx : 1;
u8 is_i915g : 1;
u8 is_i945gm : 1;
u8 is_g33 : 1;
@@ -230,6 +231,7 @@ struct intel_device_info {
u8 is_broadwater : 1;
u8 is_crestline : 1;
u8 is_ivybridge : 1;
+ u8 is_sandybridge : 1;
u8 has_fbc : 1;
u8 has_pipe_cxsr : 1;
u8 has_hotplug : 1;
@@ -915,10 +917,13 @@ enum intel_chip_family {
#define IS_845G(dev) ((dev)->pci_device == 0x2562)
#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
+#define IS_I8XX(dev) (INTEL_INFO(dev)->is_i8xx)
#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
+#define IS_I915(dev) (IS_I915G(dev) || IS_I915GM(dev))
#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
+#define IS_I945(dev) (IS_I945G(dev) || IS_I945GM(dev))
#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
@@ -927,8 +932,10 @@ enum intel_chip_family {
#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
+#define IS_I915_DISPLAY(dev) (IS_I915(dev) || IS_I945(dev) || IS_G33(dev))
#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
+#define IS_SANDYBRIDGE(dev) (INTEL_INFO(dev)->is_sandybridge)
#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index bd99216..a1c9893 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -96,7 +96,7 @@ intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
static inline u32 /* units of 100MHz */
intel_fdi_link_freq(struct drm_device *dev)
{
- if (IS_GEN5(dev)) {
+ if (IS_IRONLAKE_D(dev) || IS_IRONLAKE_M(dev)) {
struct drm_i915_private *dev_priv = dev->dev_private;
return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
} else
@@ -425,7 +425,7 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
limit = &intel_limits_pineview_lvds;
else
limit = &intel_limits_pineview_sdvo;
- } else if (!IS_GEN2(dev)) {
+ } else if (!IS_I8XX(dev)) {
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
limit = &intel_limits_i9xx_lvds;
else
@@ -1602,7 +1602,7 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
/* enable it... */
I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
- if (IS_GEN6(dev)) {
+ if (IS_SANDYBRIDGE(dev)) {
I915_WRITE(SNB_DPFC_CTL_SA,
SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
@@ -2056,7 +2056,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
/* enable normal train */
reg = FDI_TX_CTL(pipe);
temp = I915_READ(reg);
- if (IS_GEN6(dev)) {
+ if (IS_SANDYBRIDGE(dev)) {
temp &= ~FDI_LINK_TRAIN_NONE;
temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
} else if (IS_IVYBRIDGE(dev)) {
@@ -2264,7 +2264,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
temp = I915_READ(reg);
temp &= ~FDI_LINK_TRAIN_NONE;
temp |= FDI_LINK_TRAIN_PATTERN_2;
- if (IS_GEN6(dev)) {
+ if (IS_SANDYBRIDGE(dev)) {
temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
/* SNB-B */
temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
@@ -2527,7 +2527,7 @@ static void intel_clear_scanline_wait(struct drm_device *dev)
struct intel_ring_buffer *ring;
u32 tmp;
- if (IS_GEN2(dev))
+ if (IS_I8XX(dev))
/* Can't break the hang on i8xx */
return;
@@ -3852,7 +3852,7 @@ static void i9xx_update_wm(struct drm_device *dev)
if (IS_I945GM(dev))
wm_info = &i945_wm_info;
- else if (!IS_GEN2(dev))
+ else if (!IS_I8XX(dev))
wm_info = &i915_wm_info;
else
wm_info = &i855_wm_info;
@@ -4407,7 +4407,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
refclk = dev_priv->lvds_ssc_freq * 1000;
DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
refclk / 1000);
- } else if (!IS_GEN2(dev)) {
+ } else if (!IS_I8XX(dev)) {
refclk = 96000;
} else {
refclk = 48000;
@@ -4479,7 +4479,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
dpll = DPLL_VGA_MODE_DIS;
- if (!IS_GEN2(dev)) {
+ if (!IS_I8XX(dev)) {
if (is_lvds)
dpll |= DPLLB_MODE_LVDS;
else
@@ -5251,7 +5251,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
intel_wait_for_vblank(dev, pipe);
- if (IS_GEN5(dev)) {
+ if (IS_I8XX(dev)) {
/* enable address swizzle for tiling buffer */
temp = I915_READ(DISP_ARB_CTL);
I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
@@ -5506,7 +5506,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
addr = obj->phys_obj->handle->busaddr;
}
- if (IS_GEN2(dev))
+ if (IS_I8XX(dev))
I915_WRITE(CURSIZE, (height << 12) | width);
finish:
@@ -5863,7 +5863,7 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
}
- if (!IS_GEN2(dev)) {
+ if (!IS_I8XX(dev)) {
if (IS_PINEVIEW(dev))
clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
@@ -6357,7 +6357,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
if (ret)
goto cleanup_objs;
- if (IS_GEN3(dev) || IS_GEN2(dev)) {
+ if (IS_GEN2(dev) || IS_GEN3(dev)) {
u32 flip_mask;
/* Can't queue multiple flips, so wait for the previous
@@ -6558,7 +6558,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
/* Swap pipes & planes for FBC on pre-965 */
intel_crtc->pipe = pipe;
intel_crtc->plane = pipe;
- if (IS_MOBILE(dev) && IS_GEN3(dev)) {
+ if (IS_MOBILE(dev) && IS_I915_DISPLAY(dev)) {
DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
intel_crtc->plane = !pipe;
}
@@ -6639,7 +6639,7 @@ static bool has_edp_a(struct drm_device *dev)
if ((I915_READ(DP_A) & DP_DETECTED) == 0)
return false;
- if (IS_GEN5(dev) &&
+ if ((IS_IRONLAKE_D(dev) || IS_IRONLAKE_M(dev)) &&
(I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
return false;
@@ -6737,7 +6737,7 @@ static void intel_setup_outputs(struct drm_device *dev)
DRM_DEBUG_KMS("probing DP_D\n");
intel_dp_init(dev, DP_D);
}
- } else if (IS_GEN2(dev))
+ } else if (IS_I8XX(dev))
intel_dvo_init(dev);
if (SUPPORTS_TV(dev))
@@ -7559,7 +7559,7 @@ static void intel_init_display(struct drm_device *dev)
/* For FIFO watermark updates */
if (HAS_PCH_SPLIT(dev)) {
- if (IS_GEN5(dev)) {
+ if (IS_IRONLAKE_D(dev) || IS_IRONLAKE_M(dev)) {
if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
dev_priv->display.update_wm = ironlake_update_wm;
else {
@@ -7569,7 +7569,7 @@ static void intel_init_display(struct drm_device *dev)
}
dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
- } else if (IS_GEN6(dev)) {
+ } else if (IS_SANDYBRIDGE(dev)) {
if (SNB_READ_WM0_LATENCY()) {
dev_priv->display.update_wm = sandybridge_update_wm;
} else {
@@ -7611,13 +7611,13 @@ static void intel_init_display(struct drm_device *dev)
} else if (IS_G4X(dev)) {
dev_priv->display.update_wm = g4x_update_wm;
dev_priv->display.init_clock_gating = g4x_init_clock_gating;
- } else if (IS_GEN4(dev)) {
+ } else if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
dev_priv->display.update_wm = i965_update_wm;
if (IS_CRESTLINE(dev))
dev_priv->display.init_clock_gating = crestline_init_clock_gating;
else if (IS_BROADWATER(dev))
dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
- } else if (IS_GEN3(dev)) {
+ } else if (IS_I915_DISPLAY(dev)) {
dev_priv->display.update_wm = i9xx_update_wm;
dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
dev_priv->display.init_clock_gating = gen3_init_clock_gating;
@@ -7738,10 +7738,10 @@ void intel_modeset_init(struct drm_device *dev)
intel_init_display(dev);
- if (IS_GEN2(dev)) {
+ if (IS_I8XX(dev)) {
dev->mode_config.max_width = 2048;
dev->mode_config.max_height = 2048;
- } else if (IS_GEN3(dev)) {
+ } else if (IS_I915_DISPLAY(dev)) {
dev->mode_config.max_width = 4096;
dev->mode_config.max_height = 4096;
} else {
@@ -7769,7 +7769,7 @@ void intel_modeset_init(struct drm_device *dev)
intel_init_emon(dev);
}
- if (IS_GEN6(dev))
+ if (IS_SANDYBRIDGE(dev))
gen6_enable_rps(dev_priv);
if (IS_IRONLAKE_M(dev))
@@ -7808,7 +7808,7 @@ void intel_modeset_cleanup(struct drm_device *dev)
if (IS_IRONLAKE_M(dev))
ironlake_disable_drps(dev);
- if (IS_GEN6(dev))
+ if (IS_SANDYBRIDGE(dev))
gen6_disable_rps(dev);
if (IS_IRONLAKE_M(dev))
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a4d8031..ab80b15 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -303,7 +303,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
* clock divider.
*/
if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
- if (IS_GEN6(dev))
+ if (IS_SANDYBRIDGE(dev))
aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
else
aux_clock_divider = 225; /* eDP input clock at 450Mhz */
@@ -312,7 +312,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
else
aux_clock_divider = intel_hrawclk(dev) / 2;
- if (IS_GEN6(dev))
+ if (IS_SANDYBRIDGE(dev))
precharge = 3;
else
precharge = 5;
@@ -1302,7 +1302,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
for (;;) {
/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
uint32_t signal_levels;
- if (IS_GEN6(dev) && is_edp(intel_dp)) {
+ if (IS_SANDYBRIDGE(dev) && is_edp(intel_dp)) {
signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
} else {
@@ -1376,7 +1376,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
break;
}
- if (IS_GEN6(dev) && is_edp(intel_dp)) {
+ if (IS_SANDYBRIDGE(dev) && is_edp(intel_dp)) {
signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
} else {
--
1.7.4.1
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