[Intel-gfx] [PATCH] drm/i915: clarify IS_GEN vs IS_<product> usage
Jesse Barnes
jbarnes at virtuousgeek.org
Mon May 9 20:42:13 CEST 2011
On Thu, 05 May 2011 23:57:56 +0100
Chris Wilson <chris at chris-wilson.co.uk> wrote:
> On Thu, 5 May 2011 15:16:45 -0700, Jesse Barnes <jbarnes at virtuousgeek.org> wrote:
> > We generally use the gen number to indicate the generation of the render
> > portion of the chip. In some cases this isn't the same as the display
> > generation (as in the case of G33 and GMA500). So codify the de facto
> > usage by converting some IS_GEN checks into product specific checks for
> > display related differences. (Note this makes me wonder about our G33
> > watermark handling; shouldn't it be like 965 not 945? I don't have one
> > to test with...).
>
> As far as I've been able to tell, the current code works... So it can't
> be too far wrong, and I don't recall any mention of deviations in the gen3
> docs.
The gen4 docs mention DevBLC in the FW* reg section though, and
indicate that it has the same programming interface as Cantiga.
Unfortunately I don't have one to test with or I'd check whether the
GM45 code works on G33 as well.
> Whilst you are in the vicinity, does it make sense to rename info->gen to
> info->render (or info->render_gen)?
Sure.
> > @@ -230,6 +231,7 @@ struct intel_device_info {
> > u8 is_broadwater : 1;
> > u8 is_crestline : 1;
> > u8 is_ivybridge : 1;
> > + u8 is_sandybridge : 1;
> > u8 has_fbc : 1;
> > u8 has_pipe_cxsr : 1;
> > u8 has_hotplug : 1;
>
> What's the sort order here? ;-)
Well apparently not alphabetical. :) I'll put snb above ivb so at
least it's a little chronological.
>
> > @@ -915,10 +917,13 @@ enum intel_chip_family {
> > #define IS_845G(dev) ((dev)->pci_device == 0x2562)
> > #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
> > #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
> > +#define IS_I8XX(dev) (INTEL_INFO(dev)->is_i8xx)
> > #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
> > #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
> > +#define IS_I915(dev) (IS_I915G(dev) || IS_I915GM(dev))
> > #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
> > #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
> > +#define IS_I945(dev) (IS_I945G(dev) || IS_I945GM(dev))
> > #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
> > #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
> > #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
> > @@ -927,8 +932,10 @@ enum intel_chip_family {
> > #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
> > #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
> > #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
> > +#define IS_I915_DISPLAY(dev) (IS_I915(dev) || IS_I945(dev) || IS_G33(dev))
>
> Not more nested predicates that mix capability bits and devids - just add
> a new bit for the display engine! IS_I915_DISPLAY() is a good name, and
> makes me want IS_I830_DISPLAY rather than IS_I8XX. And I think you've just
> set a new precedent to distinguish the display engines from the render
> engine from the chipsets. Don't let me stop you from completing the job ;)
Ok will do. How does this one look? (Probably need to split this into
two at least, plus fixing some of the render_gen checks to make them
look for the appropriate display class).
--
Jesse Barnes, Intel Open Source Technology Center
From 3c8c2542d8ea6086ba4535e84d18b88a71dd637a Mon Sep 17 00:00:00 2001
From: Jesse Barnes <jbarnes at virtuousgeek.org>
Date: Thu, 5 May 2011 15:13:11 -0700
Subject: [PATCH] drm/i915: clarify IS_GEN vs IS_<product> usage
We generally use the gen number to indicate the generation of the render
portion of the chip. In some cases this isn't the same as the display
generation (as in the case of G33 and GMA500). So codify the de facto
usage by converting some IS_GEN checks into product specific checks for
display related differences. (Note this makes me wonder about our G33
watermark handling; shouldn't it be like 965 not 945? I don't have one
to test with...).
Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 +-
drivers/gpu/drm/i915/i915_dma.c | 22 ++++----
drivers/gpu/drm/i915/i915_drv.c | 54 ++++++++++--------
drivers/gpu/drm/i915/i915_drv.h | 29 +++++++----
drivers/gpu/drm/i915/i915_gem.c | 16 +++---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 12 ++--
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_gem_tiling.c | 12 ++--
drivers/gpu/drm/i915/i915_irq.c | 24 ++++----
drivers/gpu/drm/i915/i915_suspend.c | 24 ++++----
drivers/gpu/drm/i915/intel_bios.c | 2 +-
drivers/gpu/drm/i915/intel_crt.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 80 ++++++++++++++--------------
drivers/gpu/drm/i915/intel_dp.c | 8 ++--
drivers/gpu/drm/i915/intel_lvds.c | 12 ++--
drivers/gpu/drm/i915/intel_overlay.c | 4 +-
drivers/gpu/drm/i915/intel_panel.c | 4 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 14 +++---
drivers/gpu/drm/i915/intel_sdvo.c | 10 ++--
drivers/gpu/drm/i915/intel_tv.c | 2 +-
20 files changed, 177 insertions(+), 162 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 1e2e87f..d6386ff 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -60,7 +60,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
struct drm_device *dev = node->minor->dev;
const struct intel_device_info *info = INTEL_INFO(dev);
- seq_printf(m, "gen: %d\n", info->gen);
+ seq_printf(m, "gen: %d\n", info->render_gen);
#define B(x) seq_printf(m, #x ": %s\n", yesno(info->x))
B(is_mobile);
B(is_i85x);
@@ -749,7 +749,7 @@ static int i915_error_state(struct seq_file *m, void *unused)
seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
seq_printf(m, "EIR: 0x%08x\n", error->eir);
seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
- if (INTEL_INFO(dev)->gen >= 6) {
+ if (INTEL_INFO(dev)->render_gen >= 6) {
seq_printf(m, "ERROR: 0x%08x\n", error->error);
seq_printf(m, "Blitter command stream:\n");
seq_printf(m, " ACTHD: 0x%08x\n", error->bcs_acthd);
@@ -769,7 +769,7 @@ static int i915_error_state(struct seq_file *m, void *unused)
seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir);
seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr);
seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone);
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->render_gen >= 4) {
seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
seq_printf(m, " INSTPS: 0x%08x\n", error->instps);
}
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 9cc1162..3b07e62 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -49,7 +49,7 @@ static void i915_write_hws_pga(struct drm_device *dev)
u32 addr;
addr = dev_priv->status_page_dmah->busaddr;
- if (INTEL_INFO(dev)->gen >= 4)
+ if (INTEL_INFO(dev)->render_gen >= 4)
addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
I915_WRITE(HWS_PGA, addr);
}
@@ -366,7 +366,7 @@ i915_emit_box(struct drm_device *dev,
return -EINVAL;
}
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->render_gen >= 4) {
ret = BEGIN_LP_RING(4);
if (ret)
return ret;
@@ -479,7 +479,7 @@ static int i915_dispatch_batchbuffer(struct drm_device * dev,
if (ret)
return ret;
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->render_gen >= 4) {
OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
OUT_RING(batch->start);
} else {
@@ -777,7 +777,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
value = 1;
break;
case I915_PARAM_HAS_EXEC_CONSTANTS:
- value = INTEL_INFO(dev)->gen >= 4;
+ value = INTEL_INFO(dev)->render_gen >= 4;
break;
case I915_PARAM_HAS_RELAXED_DELTA:
value = 1;
@@ -906,12 +906,12 @@ static int
intel_alloc_mchbar_resource(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = dev->dev_private;
- int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
+ int reg = INTEL_INFO(dev)->render_gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
u32 temp_lo, temp_hi = 0;
u64 mchbar_addr;
int ret;
- if (INTEL_INFO(dev)->gen >= 4)
+ if (INTEL_INFO(dev)->render_gen >= 4)
pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
@@ -938,7 +938,7 @@ intel_alloc_mchbar_resource(struct drm_device *dev)
return ret;
}
- if (INTEL_INFO(dev)->gen >= 4)
+ if (INTEL_INFO(dev)->render_gen >= 4)
pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
upper_32_bits(dev_priv->mch_res.start));
@@ -952,7 +952,7 @@ static void
intel_setup_mchbar(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = dev->dev_private;
- int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
+ int mchbar_reg = INTEL_INFO(dev)->render_gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
u32 temp;
bool enabled;
@@ -989,7 +989,7 @@ static void
intel_teardown_mchbar(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = dev->dev_private;
- int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
+ int mchbar_reg = INTEL_INFO(dev)->render_gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
u32 temp;
if (dev_priv->mchbar_need_disable) {
@@ -1037,7 +1037,7 @@ static unsigned long i915_stolen_to_phys(struct drm_device *dev, u32 offset)
* from the Top of Low Usable DRAM which is where the BIOS places
* the graphics stolen memory.
*/
- if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
+ if (INTEL_INFO(dev)->render_gen > 3 || IS_G33(dev)) {
/* top 32bits are reserved = 0 */
pci_read_config_dword(pdev, 0xA4, &base);
} else {
@@ -1045,7 +1045,7 @@ static unsigned long i915_stolen_to_phys(struct drm_device *dev, u32 offset)
pci_bus_read_config_dword(pdev->bus, 2, 0x5C, &base);
}
#else
- if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
+ if (INTEL_INFO(dev)->render_gen > 3 || IS_G33(dev)) {
u16 val;
pci_read_config_word(pdev, 0xb0, &val);
base = val >> 4 << 20;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 84bacc2..02f2e7b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -83,74 +83,80 @@ extern int intel_agp_enabled;
.driver_data = (unsigned long) info }
static const struct intel_device_info intel_i830_info = {
- .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
+ .render_gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
+ .is_i8xx = 1, .is_i830_display = 1,
};
static const struct intel_device_info intel_845g_info = {
- .gen = 2,
+ .render_gen = 2,
.has_overlay = 1, .overlay_needs_physical = 1,
+ .is_i8xx = 1, .is_i830_display = 1,
};
static const struct intel_device_info intel_i85x_info = {
- .gen = 2, .is_i85x = 1, .is_mobile = 1,
+ .render_gen = 2, .is_i85x = 1, .is_mobile = 1,
.cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
+ .is_i8xx = 1, .is_i830_display = 1,
};
static const struct intel_device_info intel_i865g_info = {
- .gen = 2,
+ .render_gen = 2,
.has_overlay = 1, .overlay_needs_physical = 1,
+ .is_i8xx = 1, .is_i830_display = 1,
};
static const struct intel_device_info intel_i915g_info = {
- .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
+ .render_gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
+ .is_i915_display = 1,
};
static const struct intel_device_info intel_i915gm_info = {
- .gen = 3, .is_mobile = 1,
+ .render_gen = 3, .is_mobile = 1,
.cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
- .supports_tv = 1,
+ .supports_tv = 1, .is_i915_display = 1,
};
static const struct intel_device_info intel_i945g_info = {
- .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
+ .render_gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
+ .is_i915_display = 1,
};
static const struct intel_device_info intel_i945gm_info = {
- .gen = 3, .is_i945gm = 1, .is_mobile = 1,
+ .render_gen = 3, .is_i945gm = 1, .is_mobile = 1,
.has_hotplug = 1, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
- .supports_tv = 1,
+ .supports_tv = 1, .is_i915_display = 1,
};
static const struct intel_device_info intel_i965g_info = {
- .gen = 4, .is_broadwater = 1,
+ .render_gen = 4, .is_broadwater = 1,
.has_hotplug = 1,
.has_overlay = 1,
};
static const struct intel_device_info intel_i965gm_info = {
- .gen = 4, .is_crestline = 1,
+ .render_gen = 4, .is_crestline = 1,
.is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
.has_overlay = 1,
.supports_tv = 1,
};
static const struct intel_device_info intel_g33_info = {
- .gen = 3, .is_g33 = 1,
+ .render_gen = 3, .is_g33 = 1,
.need_gfx_hws = 1, .has_hotplug = 1,
- .has_overlay = 1,
+ .has_overlay = 1, .is_i915_display = 1,
};
static const struct intel_device_info intel_g45_info = {
- .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
+ .render_gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
.has_pipe_cxsr = 1, .has_hotplug = 1,
.has_bsd_ring = 1,
};
static const struct intel_device_info intel_gm45_info = {
- .gen = 4, .is_g4x = 1,
+ .render_gen = 4, .is_g4x = 1,
.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
.has_pipe_cxsr = 1, .has_hotplug = 1,
.supports_tv = 1,
@@ -158,33 +164,33 @@ static const struct intel_device_info intel_gm45_info = {
};
static const struct intel_device_info intel_pineview_info = {
- .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
+ .render_gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
.need_gfx_hws = 1, .has_hotplug = 1,
.has_overlay = 1,
};
static const struct intel_device_info intel_ironlake_d_info = {
- .gen = 5,
+ .render_gen = 5,
.need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
.has_bsd_ring = 1,
};
static const struct intel_device_info intel_ironlake_m_info = {
- .gen = 5, .is_mobile = 1,
+ .render_gen = 5, .is_mobile = 1,
.need_gfx_hws = 1, .has_hotplug = 1,
.has_fbc = 1,
.has_bsd_ring = 1,
};
static const struct intel_device_info intel_sandybridge_d_info = {
- .gen = 6,
+ .render_gen = 6, .is_sandybridge = 1,
.need_gfx_hws = 1, .has_hotplug = 1,
.has_bsd_ring = 1,
.has_blt_ring = 1,
};
static const struct intel_device_info intel_sandybridge_m_info = {
- .gen = 6, .is_mobile = 1,
+ .render_gen = 6, .is_mobile = 1, .is_sandybridge = 1,
.need_gfx_hws = 1, .has_hotplug = 1,
.has_fbc = 1,
.has_bsd_ring = 1,
@@ -192,14 +198,14 @@ static const struct intel_device_info intel_sandybridge_m_info = {
};
static const struct intel_device_info intel_ivybridge_d_info = {
- .is_ivybridge = 1, .gen = 7,
+ .is_ivybridge = 1, .render_gen = 7,
.need_gfx_hws = 1, .has_hotplug = 1,
.has_bsd_ring = 1,
.has_blt_ring = 1,
};
static const struct intel_device_info intel_ivybridge_m_info = {
- .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
+ .is_ivybridge = 1, .render_gen = 7, .is_mobile = 1,
.need_gfx_hws = 1, .has_hotplug = 1,
.has_bsd_ring = 1,
.has_blt_ring = 1,
@@ -549,7 +555,7 @@ int i915_reset(struct drm_device *dev, u8 flags)
ret = -ENODEV;
if (get_seconds() - dev_priv->last_gpu_reset < 5) {
DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
- } else switch (INTEL_INFO(dev)->gen) {
+ } else switch (INTEL_INFO(dev)->render_gen) {
case 6:
ret = gen6_do_reset(dev, flags);
break;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c0bf7de..335698c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -218,9 +218,12 @@ struct drm_i915_display_funcs {
};
struct intel_device_info {
- u8 gen;
+ u8 render_gen;
+ u8 is_i830_display : 1;
+ u8 is_i915_display : 1;
u8 is_mobile : 1;
u8 is_i85x : 1;
+ u8 is_i8xx : 1;
u8 is_i915g : 1;
u8 is_i945gm : 1;
u8 is_g33 : 1;
@@ -229,6 +232,7 @@ struct intel_device_info {
u8 is_pineview : 1;
u8 is_broadwater : 1;
u8 is_crestline : 1;
+ u8 is_sandybridge : 1;
u8 is_ivybridge : 1;
u8 has_fbc : 1;
u8 has_pipe_cxsr : 1;
@@ -915,10 +919,13 @@ enum intel_chip_family {
#define IS_845G(dev) ((dev)->pci_device == 0x2562)
#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
+#define IS_I830_DISPLAY(dev) (INTEL_INFO(dev)->is_i830_display)
#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
+#define IS_I915(dev) (IS_I915G(dev) || IS_I915GM(dev))
#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
+#define IS_I945(dev) (IS_I945G(dev) || IS_I945GM(dev))
#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
@@ -927,8 +934,10 @@ enum intel_chip_family {
#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
+#define IS_I915_DISPLAY(dev) (INTEL_INFO(dev)->is_i915_display)
#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
+#define IS_SANDYBRIDGE(dev) (INTEL_INFO(dev)->is_sandybridge)
#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
@@ -938,12 +947,12 @@ enum intel_chip_family {
* have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
* chips, etc.).
*/
-#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
-#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
-#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
-#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
-#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
-#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
+#define IS_GEN2(dev) (INTEL_INFO(dev)->render_gen == 2)
+#define IS_GEN3(dev) (INTEL_INFO(dev)->render_gen == 3)
+#define IS_GEN4(dev) (INTEL_INFO(dev)->render_gen == 4)
+#define IS_GEN5(dev) (INTEL_INFO(dev)->render_gen == 5)
+#define IS_GEN6(dev) (INTEL_INFO(dev)->render_gen == 6)
+#define IS_GEN7(dev) (INTEL_INFO(dev)->render_gen == 7)
#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
@@ -966,7 +975,7 @@ enum intel_chip_family {
/* dsparb controlled by hw only */
#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
-#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
+#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->render_gen > 2)
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
@@ -1406,7 +1415,7 @@ static inline u32 i915_gt_read(struct drm_i915_private *dev_priv, u32 reg)
{
u32 val;
- if (dev_priv->info->gen >= 6) {
+ if (dev_priv->info->render_gen >= 6) {
__gen6_gt_force_wake_get(dev_priv);
val = I915_READ(reg);
__gen6_gt_force_wake_put(dev_priv);
@@ -1419,7 +1428,7 @@ static inline u32 i915_gt_read(struct drm_i915_private *dev_priv, u32 reg)
static inline void i915_gt_write(struct drm_i915_private *dev_priv,
u32 reg, u32 val)
{
- if (dev_priv->info->gen >= 6)
+ if (dev_priv->info->render_gen >= 6)
__gen6_gt_wait_for_fifo(dev_priv);
I915_WRITE(reg, val);
}
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index bf32527..ac26396 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1383,12 +1383,12 @@ i915_gem_get_gtt_size(struct drm_i915_gem_object *obj)
struct drm_device *dev = obj->base.dev;
uint32_t size;
- if (INTEL_INFO(dev)->gen >= 4 ||
+ if (INTEL_INFO(dev)->render_gen >= 4 ||
obj->tiling_mode == I915_TILING_NONE)
return obj->base.size;
/* Previous chips need a power-of-two fence region when tiling */
- if (INTEL_INFO(dev)->gen == 3)
+ if (INTEL_INFO(dev)->render_gen == 3)
size = 1024*1024;
else
size = 512*1024;
@@ -1415,7 +1415,7 @@ i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj)
* Minimum alignment is 4k (GTT page size), but might be greater
* if a fence register is needed for the object.
*/
- if (INTEL_INFO(dev)->gen >= 4 ||
+ if (INTEL_INFO(dev)->render_gen >= 4 ||
obj->tiling_mode == I915_TILING_NONE)
return 4096;
@@ -1443,7 +1443,7 @@ i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj)
/*
* Minimum alignment is 4k (GTT page size) for sane hw.
*/
- if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
+ if (INTEL_INFO(dev)->render_gen >= 4 || IS_G33(dev) ||
obj->tiling_mode == I915_TILING_NONE)
return 4096;
@@ -2672,7 +2672,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
update:
obj->tiling_changed = false;
- switch (INTEL_INFO(dev)->gen) {
+ switch (INTEL_INFO(dev)->render_gen) {
case 6:
ret = sandybridge_write_fence_reg(obj, pipelined);
break;
@@ -2705,7 +2705,7 @@ i915_gem_clear_fence_reg(struct drm_device *dev,
drm_i915_private_t *dev_priv = dev->dev_private;
uint32_t fence_reg = reg - dev_priv->fence_regs;
- switch (INTEL_INFO(dev)->gen) {
+ switch (INTEL_INFO(dev)->render_gen) {
case 6:
I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
break;
@@ -3850,13 +3850,13 @@ i915_gem_load(struct drm_device *dev)
if (!drm_core_check_feature(dev, DRIVER_MODESET))
dev_priv->fence_reg_start = 3;
- if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
+ if (INTEL_INFO(dev)->render_gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
dev_priv->num_fence_regs = 16;
else
dev_priv->num_fence_regs = 8;
/* Initialize fence registers to zero */
- switch (INTEL_INFO(dev)->gen) {
+ switch (INTEL_INFO(dev)->render_gen) {
case 6:
for (i = 0; i < 16; i++)
I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 20a4cc5..67159b1 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -471,7 +471,7 @@ i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
{
struct drm_i915_gem_object *obj;
int ret, retry;
- bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
+ bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->render_gen < 4;
struct list_head ordered_objects;
INIT_LIST_HEAD(&ordered_objects);
@@ -762,7 +762,7 @@ i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object *obj,
return 0;
/* XXX gpu semaphores are implicated in various hard hangs on SNB */
- if (INTEL_INFO(obj->base.dev)->gen < 6 || !i915_semaphores)
+ if (INTEL_INFO(obj->base.dev)->render_gen < 6 || !i915_semaphores)
return i915_gem_object_wait_rendering(obj);
idx = intel_ring_sync_index(from, to);
@@ -941,7 +941,7 @@ i915_gem_execbuffer_retire_commands(struct drm_device *dev,
* The sampler always gets flushed on i965 (sigh).
*/
invalidate = I915_GEM_DOMAIN_COMMAND;
- if (INTEL_INFO(dev)->gen >= 4)
+ if (INTEL_INFO(dev)->render_gen >= 4)
invalidate |= I915_GEM_DOMAIN_SAMPLER;
if (ring->flush(ring, invalidate, 0)) {
i915_gem_next_request_seqno(ring);
@@ -1013,10 +1013,10 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
case I915_EXEC_CONSTANTS_REL_SURFACE:
if (ring == &dev_priv->ring[RCS] &&
mode != dev_priv->relative_constants_mode) {
- if (INTEL_INFO(dev)->gen < 4)
+ if (INTEL_INFO(dev)->render_gen < 4)
return -EINVAL;
- if (INTEL_INFO(dev)->gen > 5 &&
+ if (INTEL_INFO(dev)->render_gen > 5 &&
mode == I915_EXEC_CONSTANTS_REL_SURFACE)
return -EINVAL;
@@ -1253,7 +1253,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
exec2_list[i].alignment = exec_list[i].alignment;
exec2_list[i].offset = exec_list[i].offset;
- if (INTEL_INFO(dev)->gen < 4)
+ if (INTEL_INFO(dev)->render_gen < 4)
exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
else
exec2_list[i].flags = 0;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e46b645..ded5621 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -35,7 +35,7 @@ static unsigned int cache_level_to_agp_type(struct drm_device *dev,
{
switch (cache_level) {
case I915_CACHE_LLC_MLC:
- if (INTEL_INFO(dev)->gen >= 6)
+ if (INTEL_INFO(dev)->render_gen >= 6)
return AGP_USER_CACHED_MEMORY_LLC_MLC;
/* Older chipsets do not have this extra level of CPU
* cacheing, so fallthrough and request the PTE simply
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 82d70fd..2d8a1b3 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -92,7 +92,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
- if (INTEL_INFO(dev)->gen >= 5) {
+ if (INTEL_INFO(dev)->render_gen >= 5) {
/* On Ironlake whatever DRAM config, GPU always do
* same swizzling setup.
*/
@@ -197,7 +197,7 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
tile_width = 512;
/* check maximum stride & object size */
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->render_gen >= 4) {
/* i965 stores the end address of the gtt mapping in the fence
* reg, so dont bother to check the size */
if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
@@ -216,7 +216,7 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
}
/* 965+ just needs multiples of tile width */
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->render_gen >= 4) {
if (stride & (tile_width - 1))
return false;
return true;
@@ -241,10 +241,10 @@ i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
if (tiling_mode == I915_TILING_NONE)
return true;
- if (INTEL_INFO(obj->base.dev)->gen >= 4)
+ if (INTEL_INFO(obj->base.dev)->render_gen >= 4)
return true;
- if (INTEL_INFO(obj->base.dev)->gen == 3) {
+ if (INTEL_INFO(obj->base.dev)->render_gen == 3) {
if (obj->gtt_offset & ~I915_FENCE_START_MASK)
return false;
} else {
@@ -256,7 +256,7 @@ i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
* Previous chips need to be aligned to the size of the smallest
* fence register that can contain the object.
*/
- if (INTEL_INFO(obj->base.dev)->gen == 3)
+ if (INTEL_INFO(obj->base.dev)->render_gen == 3)
size = 1024*1024;
else
size = 512*1024;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7cac843..33da9f6 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -125,7 +125,7 @@ void intel_enable_asle(struct drm_device *dev)
else {
i915_enable_pipestat(dev_priv, 1,
PIPE_LEGACY_BLC_EVENT_ENABLE);
- if (INTEL_INFO(dev)->gen >= 4)
+ if (INTEL_INFO(dev)->render_gen >= 4)
i915_enable_pipestat(dev_priv, 0,
PIPE_LEGACY_BLC_EVENT_ENABLE);
}
@@ -216,7 +216,7 @@ int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
/* Get vtotal. */
vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->render_gen >= 4) {
/* No obvious pixelcount register. Only query vertical
* scanout position from Display scan line register.
*/
@@ -776,7 +776,7 @@ static void i915_gem_record_fences(struct drm_device *dev,
int i;
/* Fences */
- switch (INTEL_INFO(dev)->gen) {
+ switch (INTEL_INFO(dev)->render_gen) {
case 6:
for (i = 0; i < 16; i++)
error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
@@ -868,7 +868,7 @@ static void i915_capture_error_state(struct drm_device *dev)
error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
error->instpm = I915_READ(INSTPM);
error->error = 0;
- if (INTEL_INFO(dev)->gen >= 6) {
+ if (INTEL_INFO(dev)->render_gen >= 6) {
error->error = I915_READ(ERROR_GEN6);
error->bcs_acthd = I915_READ(BCS_ACTHD);
@@ -887,7 +887,7 @@ static void i915_capture_error_state(struct drm_device *dev)
if (dev_priv->ring[VCS].get_seqno)
error->vcs_seqno = dev_priv->ring[VCS].get_seqno(&dev_priv->ring[VCS]);
}
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->render_gen >= 4) {
error->ipeir = I915_READ(IPEIR_I965);
error->ipehr = I915_READ(IPEHR_I965);
error->instdone = I915_READ(INSTDONE_I965);
@@ -1045,7 +1045,7 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
printk(KERN_ERR "instruction error\n");
printk(KERN_ERR " INSTPM: 0x%08x\n",
I915_READ(INSTPM));
- if (INTEL_INFO(dev)->gen < 4) {
+ if (INTEL_INFO(dev)->render_gen < 4) {
u32 ipeir = I915_READ(IPEIR);
printk(KERN_ERR " IPEIR: 0x%08x\n",
@@ -1151,7 +1151,7 @@ static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
/* Potential stall - if we see that the flip has happened, assume a missed interrupt */
obj = work->pending_flip_obj;
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->render_gen >= 4) {
int dspsurf = DSPSURF(intel_crtc->plane);
stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
} else {
@@ -1187,7 +1187,7 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
iir = I915_READ(IIR);
- if (INTEL_INFO(dev)->gen >= 4)
+ if (INTEL_INFO(dev)->render_gen >= 4)
vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
else
vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
@@ -1423,7 +1423,7 @@ int i915_enable_vblank(struct drm_device *dev, int pipe)
return -EINVAL;
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- if (INTEL_INFO(dev)->gen >= 4)
+ if (INTEL_INFO(dev)->render_gen >= 4)
i915_enable_pipestat(dev_priv, pipe,
PIPE_START_VBLANK_INTERRUPT_ENABLE);
else
@@ -1431,7 +1431,7 @@ int i915_enable_vblank(struct drm_device *dev, int pipe)
PIPE_VBLANK_INTERRUPT_ENABLE);
/* maintain vblank delivery even in deep C-states */
- if (dev_priv->info->gen == 3)
+ if (dev_priv->info->render_gen == 3)
I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
@@ -1479,7 +1479,7 @@ void i915_disable_vblank(struct drm_device *dev, int pipe)
unsigned long irqflags;
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- if (dev_priv->info->gen == 3)
+ if (dev_priv->info->render_gen == 3)
I915_WRITE(INSTPM,
INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS);
@@ -1634,7 +1634,7 @@ void i915_hangcheck_elapsed(unsigned long data)
return;
}
- if (INTEL_INFO(dev)->gen < 4) {
+ if (INTEL_INFO(dev)->render_gen < 4) {
acthd = I915_READ(ACTHD);
instdone = I915_READ(INSTDONE);
instdone1 = 0;
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 6cb27ff..613871f 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -266,7 +266,7 @@ static void i915_save_modeset_reg(struct drm_device *dev)
dev_priv->saveFPA1 = I915_READ(_FPA1);
dev_priv->saveDPLL_A = I915_READ(_DPLL_A);
}
- if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
+ if (INTEL_INFO(dev)->render_gen >= 4 && !HAS_PCH_SPLIT(dev))
dev_priv->saveDPLL_A_MD = I915_READ(_DPLL_A_MD);
dev_priv->saveHTOTAL_A = I915_READ(_HTOTAL_A);
dev_priv->saveHBLANK_A = I915_READ(_HBLANK_A);
@@ -304,7 +304,7 @@ static void i915_save_modeset_reg(struct drm_device *dev)
dev_priv->saveDSPASIZE = I915_READ(_DSPASIZE);
dev_priv->saveDSPAPOS = I915_READ(_DSPAPOS);
dev_priv->saveDSPAADDR = I915_READ(_DSPAADDR);
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->render_gen >= 4) {
dev_priv->saveDSPASURF = I915_READ(_DSPASURF);
dev_priv->saveDSPATILEOFF = I915_READ(_DSPATILEOFF);
}
@@ -323,7 +323,7 @@ static void i915_save_modeset_reg(struct drm_device *dev)
dev_priv->saveFPB1 = I915_READ(_FPB1);
dev_priv->saveDPLL_B = I915_READ(_DPLL_B);
}
- if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
+ if (INTEL_INFO(dev)->render_gen >= 4 && !HAS_PCH_SPLIT(dev))
dev_priv->saveDPLL_B_MD = I915_READ(_DPLL_B_MD);
dev_priv->saveHTOTAL_B = I915_READ(_HTOTAL_B);
dev_priv->saveHBLANK_B = I915_READ(_HBLANK_B);
@@ -361,7 +361,7 @@ static void i915_save_modeset_reg(struct drm_device *dev)
dev_priv->saveDSPBSIZE = I915_READ(_DSPBSIZE);
dev_priv->saveDSPBPOS = I915_READ(_DSPBPOS);
dev_priv->saveDSPBADDR = I915_READ(_DSPBADDR);
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->render_gen >= 4) {
dev_priv->saveDSPBSURF = I915_READ(_DSPBSURF);
dev_priv->saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF);
}
@@ -369,7 +369,7 @@ static void i915_save_modeset_reg(struct drm_device *dev)
dev_priv->savePIPEBSTAT = I915_READ(_PIPEBSTAT);
/* Fences */
- switch (INTEL_INFO(dev)->gen) {
+ switch (INTEL_INFO(dev)->render_gen) {
case 6:
for (i = 0; i < 16; i++)
dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
@@ -403,7 +403,7 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
return;
/* Fences */
- switch (INTEL_INFO(dev)->gen) {
+ switch (INTEL_INFO(dev)->render_gen) {
case 6:
for (i = 0; i < 16; i++)
I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->saveFENCE[i]);
@@ -459,7 +459,7 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A);
POSTING_READ(dpll_a_reg);
udelay(150);
- if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
+ if (INTEL_INFO(dev)->render_gen >= 4 && !HAS_PCH_SPLIT(dev)) {
I915_WRITE(_DPLL_A_MD, dev_priv->saveDPLL_A_MD);
POSTING_READ(_DPLL_A_MD);
}
@@ -503,7 +503,7 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
I915_WRITE(_PIPEASRC, dev_priv->savePIPEASRC);
I915_WRITE(_DSPAADDR, dev_priv->saveDSPAADDR);
I915_WRITE(_DSPASTRIDE, dev_priv->saveDSPASTRIDE);
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->render_gen >= 4) {
I915_WRITE(_DSPASURF, dev_priv->saveDSPASURF);
I915_WRITE(_DSPATILEOFF, dev_priv->saveDSPATILEOFF);
}
@@ -528,7 +528,7 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B);
POSTING_READ(dpll_b_reg);
udelay(150);
- if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
+ if (INTEL_INFO(dev)->render_gen >= 4 && !HAS_PCH_SPLIT(dev)) {
I915_WRITE(_DPLL_B_MD, dev_priv->saveDPLL_B_MD);
POSTING_READ(_DPLL_B_MD);
}
@@ -572,7 +572,7 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
I915_WRITE(_PIPEBSRC, dev_priv->savePIPEBSRC);
I915_WRITE(_DSPBADDR, dev_priv->saveDSPBADDR);
I915_WRITE(_DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->render_gen >= 4) {
I915_WRITE(_DSPBSURF, dev_priv->saveDSPBSURF);
I915_WRITE(_DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
}
@@ -628,7 +628,7 @@ void i915_save_display(struct drm_device *dev)
dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
dev_priv->saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
- if (INTEL_INFO(dev)->gen >= 4)
+ if (INTEL_INFO(dev)->render_gen >= 4)
dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
if (IS_MOBILE(dev) && !IS_I830(dev))
dev_priv->saveLVDS = I915_READ(LVDS);
@@ -719,7 +719,7 @@ void i915_restore_display(struct drm_device *dev)
I915_WRITE(ADPA, dev_priv->saveADPA);
/* LVDS state */
- if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
+ if (INTEL_INFO(dev)->render_gen >= 4 && !HAS_PCH_SPLIT(dev))
I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
if (HAS_PCH_SPLIT(dev)) {
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index fb5b4d4..48bfb5e 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -260,7 +260,7 @@ parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
static int intel_bios_ssc_frequency(struct drm_device *dev,
bool alternate)
{
- switch (INTEL_INFO(dev)->gen) {
+ switch (INTEL_INFO(dev)->render_gen) {
case 2:
return alternate ? 66 : 48;
case 3:
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index e93f93c..fab6dfa 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -140,7 +140,7 @@ static void intel_crt_mode_set(struct drm_encoder *encoder,
* Disable separate mode multiplier used when cloning SDVO to CRT
* XXX this needs to be adjusted when we really are cloning
*/
- if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
+ if (INTEL_INFO(dev)->render_gen >= 4 && !HAS_PCH_SPLIT(dev)) {
dpll_md = I915_READ(dpll_md_reg);
I915_WRITE(dpll_md_reg,
dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 95828e3..3df91bf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -96,7 +96,7 @@ intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
static inline u32 /* units of 100MHz */
intel_fdi_link_freq(struct drm_device *dev)
{
- if (IS_GEN5(dev)) {
+ if (IS_IRONLAKE_D(dev) || IS_IRONLAKE_M(dev)) {
struct drm_i915_private *dev_priv = dev->dev_private;
return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
} else
@@ -425,7 +425,7 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
limit = &intel_limits_pineview_lvds;
else
limit = &intel_limits_pineview_sdvo;
- } else if (!IS_GEN2(dev)) {
+ } else if (!IS_I830_DISPLAY(dev)) {
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
limit = &intel_limits_i9xx_lvds;
else
@@ -747,7 +747,7 @@ void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->render_gen >= 4) {
int reg = PIPECONF(pipe);
/* Wait for the Pipe State to go off */
@@ -852,7 +852,7 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
u32 val;
/* ILK FDI PLL is always enabled */
- if (dev_priv->info->gen == 5)
+ if (dev_priv->info->render_gen == 5)
return;
reg = FDI_TX_CTL(pipe);
@@ -1041,7 +1041,7 @@ static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
u32 val;
/* No really, not for ILK+ */
- BUG_ON(dev_priv->info->gen >= 5);
+ BUG_ON(dev_priv->info->render_gen >= 5);
/* PLL is protected by panel, make sure we can write it */
if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
@@ -1106,7 +1106,7 @@ static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
u32 val;
/* PCH only available on ILK+ */
- BUG_ON(dev_priv->info->gen < 5);
+ BUG_ON(dev_priv->info->render_gen < 5);
/* PCH refclock must be enabled first */
assert_pch_refclk_enabled(dev_priv);
@@ -1126,7 +1126,7 @@ static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
u32 val;
/* PCH only available on ILK+ */
- BUG_ON(dev_priv->info->gen < 5);
+ BUG_ON(dev_priv->info->render_gen < 5);
/* Make sure transcoder isn't still depending on us */
assert_transcoder_disabled(dev_priv, pipe);
@@ -1146,7 +1146,7 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
u32 val;
/* PCH only available on ILK+ */
- BUG_ON(dev_priv->info->gen < 5);
+ BUG_ON(dev_priv->info->render_gen < 5);
/* Make sure PCH DPLL is enabled */
assert_pch_pll_enabled(dev_priv, pipe);
@@ -1602,7 +1602,7 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
/* enable it... */
I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
- if (IS_GEN6(dev)) {
+ if (IS_SANDYBRIDGE(dev)) {
I915_WRITE(SNB_DPFC_CTL_SA,
SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
@@ -1794,7 +1794,7 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev,
case I915_TILING_NONE:
if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
alignment = 128 * 1024;
- else if (INTEL_INFO(dev)->gen >= 4)
+ else if (INTEL_INFO(dev)->render_gen >= 4)
alignment = 4 * 1024;
else
alignment = 64 * 1024;
@@ -1890,7 +1890,7 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
DRM_ERROR("Unknown color depth\n");
return -EINVAL;
}
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->render_gen >= 4) {
if (obj->tiling_mode != I915_TILING_NONE)
dspcntr |= DISPPLANE_TILED;
else
@@ -1909,7 +1909,7 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
Start, Offset, x, y, fb->pitch);
I915_WRITE(DSPSTRIDE(plane), fb->pitch);
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->render_gen >= 4) {
I915_WRITE(DSPSURF(plane), Start);
I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
I915_WRITE(DSPADDR(plane), Offset);
@@ -2056,7 +2056,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
/* enable normal train */
reg = FDI_TX_CTL(pipe);
temp = I915_READ(reg);
- if (IS_GEN6(dev)) {
+ if (IS_SANDYBRIDGE(dev)) {
temp &= ~FDI_LINK_TRAIN_NONE;
temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
} else if (IS_IVYBRIDGE(dev)) {
@@ -2264,7 +2264,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
temp = I915_READ(reg);
temp &= ~FDI_LINK_TRAIN_NONE;
temp |= FDI_LINK_TRAIN_PATTERN_2;
- if (IS_GEN6(dev)) {
+ if (IS_SANDYBRIDGE(dev)) {
temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
/* SNB-B */
temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
@@ -2527,7 +2527,7 @@ static void intel_clear_scanline_wait(struct drm_device *dev)
struct intel_ring_buffer *ring;
u32 tmp;
- if (IS_GEN2(dev))
+ if (IS_I830_DISPLAY(dev))
/* Can't break the hang on i8xx */
return;
@@ -3852,7 +3852,7 @@ static void i9xx_update_wm(struct drm_device *dev)
if (IS_I945GM(dev))
wm_info = &i945_wm_info;
- else if (!IS_GEN2(dev))
+ else if (!IS_I830_DISPLAY(dev))
wm_info = &i915_wm_info;
else
wm_info = &i855_wm_info;
@@ -4407,7 +4407,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
refclk = dev_priv->lvds_ssc_freq * 1000;
DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
refclk / 1000);
- } else if (!IS_GEN2(dev)) {
+ } else if (!IS_I830_DISPLAY(dev)) {
refclk = 96000;
} else {
refclk = 48000;
@@ -4479,7 +4479,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
dpll = DPLL_VGA_MODE_DIS;
- if (!IS_GEN2(dev)) {
+ if (!IS_I830_DISPLAY(dev)) {
if (is_lvds)
dpll |= DPLLB_MODE_LVDS;
else
@@ -4517,7 +4517,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
break;
}
- if (INTEL_INFO(dev)->gen >= 4)
+ if (INTEL_INFO(dev)->render_gen >= 4)
dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
} else {
if (is_lvds) {
@@ -4556,7 +4556,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
else
dspcntr |= DISPPLANE_SEL_PIPE_B;
- if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
+ if (pipe == 0 && INTEL_INFO(dev)->render_gen < 4) {
/* Enable pixel doubling when the dot clock is > 90% of the (display)
* core speed.
*
@@ -4608,7 +4608,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
* panels behave in the two modes.
*/
/* set the dithering flag on LVDS as needed */
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->render_gen >= 4) {
if (dev_priv->lvds_dither)
temp |= LVDS_ENABLE_DITHER;
else
@@ -4643,7 +4643,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
POSTING_READ(DPLL(pipe));
udelay(150);
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->render_gen >= 4) {
temp = 0;
if (is_sdvo) {
temp = intel_mode_get_pixel_multiplier(adjusted_mode);
@@ -5251,7 +5251,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
intel_wait_for_vblank(dev, pipe);
- if (IS_GEN5(dev)) {
+ if (IS_I830_DISPLAY(dev)) {
/* enable address swizzle for tiling buffer */
temp = I915_READ(DISP_ARB_CTL);
I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
@@ -5506,7 +5506,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
addr = obj->phys_obj->handle->busaddr;
}
- if (IS_GEN2(dev))
+ if (IS_I830_DISPLAY(dev))
I915_WRITE(CURSIZE, (height << 12) | width);
finish:
@@ -5863,7 +5863,7 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
}
- if (!IS_GEN2(dev)) {
+ if (!IS_I830_DISPLAY(dev)) {
if (IS_PINEVIEW(dev))
clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
@@ -6357,7 +6357,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
if (ret)
goto cleanup_objs;
- if (IS_GEN3(dev) || IS_GEN2(dev)) {
+ if (IS_GEN2(dev) || IS_GEN3(dev)) {
u32 flip_mask;
/* Can't queue multiple flips, so wait for the previous
@@ -6392,7 +6392,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
*/
atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
- switch (INTEL_INFO(dev)->gen) {
+ switch (INTEL_INFO(dev)->render_gen) {
case 2:
OUT_RING(MI_DISPLAY_FLIP |
MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
@@ -6558,7 +6558,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
/* Swap pipes & planes for FBC on pre-965 */
intel_crtc->pipe = pipe;
intel_crtc->plane = pipe;
- if (IS_MOBILE(dev) && IS_GEN3(dev)) {
+ if (IS_MOBILE(dev) && IS_I915_DISPLAY(dev)) {
DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
intel_crtc->plane = !pipe;
}
@@ -6639,7 +6639,7 @@ static bool has_edp_a(struct drm_device *dev)
if ((I915_READ(DP_A) & DP_DETECTED) == 0)
return false;
- if (IS_GEN5(dev) &&
+ if ((IS_IRONLAKE_D(dev) || IS_IRONLAKE_M(dev)) &&
(I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
return false;
@@ -6737,7 +6737,7 @@ static void intel_setup_outputs(struct drm_device *dev)
DRM_DEBUG_KMS("probing DP_D\n");
intel_dp_init(dev, DP_D);
}
- } else if (IS_GEN2(dev))
+ } else if (IS_I830_DISPLAY(dev))
intel_dvo_init(dev);
if (SUPPORTS_TV(dev))
@@ -7559,7 +7559,7 @@ static void intel_init_display(struct drm_device *dev)
/* For FIFO watermark updates */
if (HAS_PCH_SPLIT(dev)) {
- if (IS_GEN5(dev)) {
+ if (IS_IRONLAKE_D(dev) || IS_IRONLAKE_M(dev)) {
if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
dev_priv->display.update_wm = ironlake_update_wm;
else {
@@ -7569,7 +7569,7 @@ static void intel_init_display(struct drm_device *dev)
}
dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
- } else if (IS_GEN6(dev)) {
+ } else if (IS_SANDYBRIDGE(dev)) {
if (SNB_READ_WM0_LATENCY()) {
dev_priv->display.update_wm = sandybridge_update_wm;
} else {
@@ -7611,13 +7611,13 @@ static void intel_init_display(struct drm_device *dev)
} else if (IS_G4X(dev)) {
dev_priv->display.update_wm = g4x_update_wm;
dev_priv->display.init_clock_gating = g4x_init_clock_gating;
- } else if (IS_GEN4(dev)) {
+ } else if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
dev_priv->display.update_wm = i965_update_wm;
if (IS_CRESTLINE(dev))
dev_priv->display.init_clock_gating = crestline_init_clock_gating;
else if (IS_BROADWATER(dev))
dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
- } else if (IS_GEN3(dev)) {
+ } else if (IS_I915_DISPLAY(dev)) {
dev_priv->display.update_wm = i9xx_update_wm;
dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
dev_priv->display.init_clock_gating = gen3_init_clock_gating;
@@ -7738,10 +7738,10 @@ void intel_modeset_init(struct drm_device *dev)
intel_init_display(dev);
- if (IS_GEN2(dev)) {
+ if (IS_I830_DISPLAY(dev)) {
dev->mode_config.max_width = 2048;
dev->mode_config.max_height = 2048;
- } else if (IS_GEN3(dev)) {
+ } else if (IS_I915_DISPLAY(dev)) {
dev->mode_config.max_width = 4096;
dev->mode_config.max_height = 4096;
} else {
@@ -7769,7 +7769,7 @@ void intel_modeset_init(struct drm_device *dev)
intel_init_emon(dev);
}
- if (IS_GEN6(dev))
+ if (IS_SANDYBRIDGE(dev))
gen6_enable_rps(dev_priv);
if (IS_IRONLAKE_M(dev))
@@ -7808,7 +7808,7 @@ void intel_modeset_cleanup(struct drm_device *dev)
if (IS_IRONLAKE_M(dev))
ironlake_disable_drps(dev);
- if (IS_GEN6(dev))
+ if (IS_SANDYBRIDGE(dev))
gen6_disable_rps(dev);
if (IS_IRONLAKE_M(dev))
@@ -7920,7 +7920,7 @@ intel_display_capture_error_state(struct drm_device *dev)
error->plane[i].size = I915_READ(DSPSIZE(i));
error->plane[i].pos= I915_READ(DSPPOS(i));
error->plane[i].addr = I915_READ(DSPADDR(i));
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->render_gen >= 4) {
error->plane[i].surface = I915_READ(DSPSURF(i));
error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
}
@@ -7962,7 +7962,7 @@ intel_display_print_error_state(struct seq_file *m,
seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
seq_printf(m, " POS: %08x\n", error->plane[i].pos);
seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->render_gen >= 4) {
seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a4d8031..ab80b15 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -303,7 +303,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
* clock divider.
*/
if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
- if (IS_GEN6(dev))
+ if (IS_SANDYBRIDGE(dev))
aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
else
aux_clock_divider = 225; /* eDP input clock at 450Mhz */
@@ -312,7 +312,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
else
aux_clock_divider = intel_hrawclk(dev) / 2;
- if (IS_GEN6(dev))
+ if (IS_SANDYBRIDGE(dev))
precharge = 3;
else
precharge = 5;
@@ -1302,7 +1302,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
for (;;) {
/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
uint32_t signal_levels;
- if (IS_GEN6(dev) && is_edp(intel_dp)) {
+ if (IS_SANDYBRIDGE(dev) && is_edp(intel_dp)) {
signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
} else {
@@ -1376,7 +1376,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
break;
}
- if (IS_GEN6(dev) && is_edp(intel_dp)) {
+ if (IS_SANDYBRIDGE(dev) && is_edp(intel_dp)) {
signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
} else {
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 67cb076..387fe61 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -234,7 +234,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
int pipe;
/* Should never happen!! */
- if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
+ if (INTEL_INFO(dev)->render_gen < 4 && intel_crtc->pipe == 0) {
DRM_ERROR("Can't support LVDS on pipe A\n");
return false;
}
@@ -268,7 +268,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
goto out;
/* 965+ wants fuzzy fitting */
- if (INTEL_INFO(dev)->gen >= 4)
+ if (INTEL_INFO(dev)->render_gen >= 4)
pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
PFIT_FILTER_FUZZY);
@@ -294,7 +294,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
case DRM_MODE_SCALE_ASPECT:
/* Scale but preserve the aspect ratio */
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->render_gen >= 4) {
u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
@@ -354,7 +354,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
if (mode->vdisplay != adjusted_mode->vdisplay ||
mode->hdisplay != adjusted_mode->hdisplay) {
pfit_control |= PFIT_ENABLE;
- if (INTEL_INFO(dev)->gen >= 4)
+ if (INTEL_INFO(dev)->render_gen >= 4)
pfit_control |= PFIT_SCALING_AUTO;
else
pfit_control |= (VERT_AUTO_SCALE |
@@ -376,7 +376,7 @@ out:
}
/* Make sure pre-965 set dither correctly */
- if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither)
+ if (INTEL_INFO(dev)->render_gen < 4 && dev_priv->lvds_dither)
pfit_control |= PANEL_8TO6_DITHER_ENABLE;
if (pfit_control != intel_lvds->pfit_control ||
@@ -901,7 +901,7 @@ bool intel_lvds_init(struct drm_device *dev)
intel_encoder->clone_mask = (1 << INTEL_LVDS_CLONE_BIT);
intel_encoder->crtc_mask = (1 << 1);
- if (INTEL_INFO(dev)->gen >= 5)
+ if (INTEL_INFO(dev)->render_gen >= 5)
intel_encoder->crtc_mask |= (1 << 0);
drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index a670c00..b65225f 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -903,7 +903,7 @@ static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
return -EINVAL;
/* can't use the overlay with double wide pipe */
- if (INTEL_INFO(overlay->dev)->gen < 4 &&
+ if (INTEL_INFO(overlay->dev)->render_gen < 4 &&
(I915_READ(PIPECONF(crtc->pipe)) & (PIPECONF_DOUBLE_WIDE | PIPECONF_ENABLE)) != PIPECONF_ENABLE)
return -EINVAL;
@@ -920,7 +920,7 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
/* XXX: This is not the same logic as in the xorg driver, but more in
* line with the intel documentation for the i965
*/
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->render_gen >= 4) {
/* on i965 use the PGM reg to read out the autoscaler values */
ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
} else {
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index a06ff07..70fad6e 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -116,7 +116,7 @@ static int is_backlight_combination_mode(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- if (INTEL_INFO(dev)->gen >= 4)
+ if (INTEL_INFO(dev)->render_gen >= 4)
return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
if (IS_GEN2(dev))
@@ -178,7 +178,7 @@ u32 intel_panel_get_max_backlight(struct drm_device *dev)
max >>= 17;
} else {
max >>= 16;
- if (INTEL_INFO(dev)->gen < 4)
+ if (INTEL_INFO(dev)->render_gen < 4)
max &= ~1;
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 12c168f..4296b23 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -97,7 +97,7 @@ render_ring_flush(struct intel_ring_buffer *ring,
if ((invalidate_domains|flush_domains) &
I915_GEM_DOMAIN_RENDER)
cmd &= ~MI_NO_WRITE_FLUSH;
- if (INTEL_INFO(dev)->gen < 4) {
+ if (INTEL_INFO(dev)->render_gen < 4) {
/*
* On the 965, the sampler cache always gets flushed
* and this bit is reserved.
@@ -133,7 +133,7 @@ static void ring_write_tail(struct intel_ring_buffer *ring,
u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
{
drm_i915_private_t *dev_priv = ring->dev->dev_private;
- u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
+ u32 acthd_reg = INTEL_INFO(ring->dev)->render_gen >= 4 ?
RING_ACTHD(ring->mmio_base) : ACTHD;
return I915_READ(acthd_reg);
@@ -284,14 +284,14 @@ static int init_render_ring(struct intel_ring_buffer *ring)
struct drm_i915_private *dev_priv = dev->dev_private;
int ret = init_ring_common(ring);
- if (INTEL_INFO(dev)->gen > 3) {
+ if (INTEL_INFO(dev)->render_gen > 3) {
int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
if (IS_GEN6(dev) || IS_GEN7(dev))
mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
I915_WRITE(MI_MODE, mode);
}
- if (INTEL_INFO(dev)->gen >= 6) {
+ if (INTEL_INFO(dev)->render_gen >= 6) {
} else if (IS_GEN5(dev)) {
ret = init_pipe_control(ring);
if (ret)
@@ -713,7 +713,7 @@ render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
if (ret)
return ret;
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->render_gen >= 4) {
intel_ring_emit(ring,
MI_BATCH_BUFFER_START | (2 << 6) |
MI_BATCH_NON_SECURE_I965);
@@ -1270,7 +1270,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
*ring = render_ring;
- if (INTEL_INFO(dev)->gen >= 6) {
+ if (INTEL_INFO(dev)->render_gen >= 6) {
ring->add_request = gen6_add_request;
ring->irq_get = gen6_render_ring_get_irq;
ring->irq_put = gen6_render_ring_put_irq;
@@ -1293,7 +1293,7 @@ int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
*ring = render_ring;
- if (INTEL_INFO(dev)->gen >= 6) {
+ if (INTEL_INFO(dev)->render_gen >= 6) {
ring->add_request = gen6_add_request;
ring->irq_get = gen6_render_ring_get_irq;
ring->irq_put = gen6_render_ring_put_irq;
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 4324f33..29abaa1 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1060,11 +1060,11 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
return;
/* Set the SDVO control regs. */
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->render_gen >= 4) {
sdvox = 0;
if (intel_sdvo->is_hdmi)
sdvox |= intel_sdvo->color_range;
- if (INTEL_INFO(dev)->gen < 5)
+ if (INTEL_INFO(dev)->render_gen < 5)
sdvox |= SDVO_BORDER_ENABLE;
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
@@ -1087,7 +1087,7 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
if (intel_sdvo->has_hdmi_audio)
sdvox |= SDVO_AUDIO_ENABLE;
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->render_gen >= 4) {
/* done in crtc_mode_set as the dpll_md reg must be written early */
} else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
/* done in crtc_mode_set as it lives inside the dpll register */
@@ -1096,7 +1096,7 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
}
if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
- INTEL_INFO(dev)->gen < 5)
+ INTEL_INFO(dev)->render_gen < 5)
sdvox |= SDVO_STALL_SELECT;
intel_sdvo_write_sdvox(intel_sdvo, sdvox);
}
@@ -2046,7 +2046,7 @@ intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
connector->force_audio_property, 0);
}
- if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
+ if (INTEL_INFO(dev)->render_gen >= 4 && IS_MOBILE(dev))
intel_attach_broadcast_rgb_property(&connector->base.base);
}
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 529f232..565f744 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1140,7 +1140,7 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
color_conversion->av);
}
- if (INTEL_INFO(dev)->gen >= 4)
+ if (INTEL_INFO(dev)->render_gen >= 4)
I915_WRITE(TV_CLR_KNOBS, 0x00404000);
else
I915_WRITE(TV_CLR_KNOBS, 0x00606000);
--
1.7.4.1
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