[Intel-gfx] [PATCH] drm/i915: Update the location of the ringbuffers' HWS_PGA registers for IVB.

[Xiang, Haihao]

On Wed, 2011-05-11 at 02:24 +0800, Eric Anholt wrote:
> They have been moved from the ringbuffer groups to their own group it
> looks like.  Fixes GPU hangs on gnome startup.
> 
> Signed-off-by: Eric Anholt <eric at anholt.net>
> ---
>  drivers/gpu/drm/i915/i915_reg.h         |    3 +++
>  drivers/gpu/drm/i915/intel_ringbuffer.c |   27 ++++++++++++++++++++++++---
>  2 files changed, 27 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f12c291..9cb6353 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -291,6 +291,9 @@
>  #define RING_MAX_IDLE(base)	((base)+0x54)
>  #define RING_HWS_PGA(base)	((base)+0x80)
>  #define RING_HWS_PGA_GEN6(base)	((base)+0x2080)
> +#define RENDER_HWS_PGA_GEN7	(0x04080)
> +#define BSD_HWS_PGA_GEN7	(0x04180)
The documents says the BSD HWS_PGA register is 0x4180 since GEN6, but we
found 0x4180 causes GPU hang when using BSD ring, however BSD ring works
fine with 0x14080.  I am not sure whether GEN7 has the same problem or
not. Currently we have not machine, could you help to verify it?


> +#define BLT_HWS_PGA_GEN7	(0x04280)
>  #define RING_ACTHD(base)	((base)+0x74)
>  #define RING_NOPID(base)	((base)+0x94)
>  #define RING_IMR(base)		((base)+0xa8)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index a32dc71..5edb512 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -551,10 +551,31 @@ render_ring_put_irq(struct intel_ring_buffer *ring)
>  
>  void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
>  {
> +	struct drm_device *dev = ring->dev;
>  	drm_i915_private_t *dev_priv = ring->dev->dev_private;
> -	u32 mmio = (IS_GEN6(ring->dev) || IS_GEN7(ring->dev)) ?
> -		RING_HWS_PGA_GEN6(ring->mmio_base) :
> -		RING_HWS_PGA(ring->mmio_base);
> +	u32 mmio = 0;
> +
> +	/* The ring status page addresses are no longer next to the rest of
> +	 * the ring registers as of gen7.
> +	 */
> +	if (IS_GEN7(dev)) {
> +		switch (ring->id) {
> +		case RING_RENDER:
> +			mmio = RENDER_HWS_PGA_GEN7;
> +			break;
> +		case RING_BLT:
> +			mmio = BLT_HWS_PGA_GEN7;
> +			break;
> +		case RING_BSD:
> +			mmio = BSD_HWS_PGA_GEN7;
> +			break;
> +		}
> +	} else if (IS_GEN6(ring->dev)) {
> +		mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
> +	} else {
> +		mmio = RING_HWS_PGA(ring->mmio_base);
> +	}
> +
>  	I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
>  	POSTING_READ(mmio);
>  }