[Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places
Keith Packard
keithp at keithp.com
Wed Nov 2 21:05:23 CET 2011
On Wed, 02 Nov 2011 15:36:20 -0400, Adam Jackson <ajax at redhat.com> wrote:
> The VBT is going to be crap.
The only question then is what to do with hardware that doesn't have the
DPCD value -- that's "new" in revision 0x11, after all.
How about this:
commit 34ebe02cc78f20ae6b7865c5087c3b5ac7810185
Author: Keith Packard <keithp at keithp.com>
Date: Wed Nov 2 13:03:47 2011 -0700
drm/i915: Use DPCD value for max DP lanes where possible
Fall back to the VBT value for eDP monitors only when DPCD is missing
the value.
Signed-off-by: Keith Packard <keithp at keithp.com>
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 02b56ce..93b082a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -154,6 +154,8 @@ intel_edp_link_config(struct intel_encoder *intel_encoder,
static int
intel_dp_max_lane_count(struct intel_dp *intel_dp)
{
+ struct drm_device *dev = intel_dp->base.base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
int max_lane_count = 4;
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
@@ -164,6 +166,8 @@ intel_dp_max_lane_count(struct intel_dp *intel_dp)
default:
max_lane_count = 4;
}
+ } else if (is_edp(intel_dp)) {
+ max_lane_count = dev_priv->edp.lanes;
}
return max_lane_count;
}
@@ -765,12 +769,11 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
continue;
intel_dp = enc_to_intel_dp(encoder);
- if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || is_pch_edp(intel_dp)) {
+ if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
+ intel_dp->base.type == INTEL_OUTPUT_EDP)
+ {
lane_count = intel_dp->lane_count;
break;
- } else if (is_cpu_edp(intel_dp)) {
- lane_count = dev_priv->edp.lanes;
- break;
}
}
--
keith.packard at intel.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 827 bytes
Desc: not available
URL: <http://lists.freedesktop.org/archives/intel-gfx/attachments/20111102/cb2a29b6/attachment.sig>
More information about the Intel-gfx
mailing list