[Intel-gfx] [PATCH v5] drm/i915: pass ELD to HDMI/DP audio driver
Christopher White
c.white at pulseforce.com
Thu Nov 10 12:00:53 CET 2011
On 11/10/11 9:55 AM, Christopher White wrote:
> On 11/10/11 8:55 AM, Wu Fengguang wrote:
>> On Thu, Nov 10, 2011 at 03:33:50PM +0800, Wu Fengguang wrote:
>>> Wow I reproduced the bug and got a very interesting dmesg:
>>>
>>> gfx => [ 4561.287980] [drm:intel_write_eld], ELD on
>>> [CONNECTOR:12:HDMI-A-2], [ENCODER:11:TMDS-11]
>>> gfx => [ 4561.291730] [drm:ironlake_write_eld], ELD on pipe B
>>> gfx => [ 4561.293804] [drm:ironlake_write_eld], Audio
>>> directed to unknown port
>>> gfx => [ 4561.295273] [drm:ironlake_write_eld],
>>> alsa => [ 4561.295486] HDMI hot plug event: Codec=3 Pin=6
>>> Presence_Detect=1 ELD_Valid=0
>>> alsa => [ 4561.295564] HDMI status: Codec=3 Pin=6
>>> Presence_Detect=1 ELD_Valid=0
>>> gfx => [ 4561.300020] ELD size 13
>>> alsa => [ 4561.300697] HDMI hot plug event: Codec=3 Pin=6
>>> Presence_Detect=1 ELD_Valid=1
>>> alsa => [ 4561.303322] HDMI status: Codec=3 Pin=6
>>> Presence_Detect=1 ELD_Valid=1
>>> alsa => [ 4561.311120] ALSA hda_eld.c:259 HDMI: Unknown ELD
>>> version 0
>>>
>>> Hey the two parts are interleaved!
>>>
>>> But still it should work all fine, since the gfx driver does
>>>
>>> set ELD_Valid = 0
>>> write ELD
>>> set ELD_Valid = 1
>>>
>>> So the audio driver would read the correct ELD unless the ELD content
>>> and flag writes are somehow _reordered_ underneath. Or the ELD content
>>> writes take some time to take effect?
>> Just confirmed that adding 1s delay can fix it!
>>
>> New dmesg is:
>>
>> [ 48.564923] [drm:drm_crtc_helper_set_mode], [ENCODER:11:TMDS-11]
>> set [MODE:34:]
>> [ 48.567481] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe B
>> [ 48.568975] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-2],
>> [ENCODER:11:TMDS-11]
>> [ 48.571728] [drm:ironlake_write_eld], ELD on pipe B
>> [ 48.572882] [drm:ironlake_write_eld], Audio directed to unknown port
>> [ 48.575252] [drm:ironlake_write_eld],
>> [ 48.575400] HDMI hot plug event: Codec=3 Pin=6 Presence_Detect=1
>> ELD_Valid=0
>> [ 48.575487] HDMI status: Codec=3 Pin=6 Presence_Detect=1 ELD_Valid=0
>> [ 48.580116] ELD size 13
>> [ 48.580795] HDMI hot plug event: Codec=3 Pin=6 Presence_Detect=1
>> ELD_Valid=1
>> [ 48.583340] HDMI status: Codec=3 Pin=6 Presence_Detect=1 ELD_Valid=1
>> [ 48.632514] [drm:intel_wait_for_vblank], vblank wait timed out
>> [ 48.685322] [drm:intel_wait_for_vblank], vblank wait timed out
>> [ 48.687438] [drm:ironlake_update_wm], FIFO watermarks For pipe A -
>> plane 5, cursor: 6
>> [ 48.687438] [drm:ironlake_update_wm], FIFO watermarks For pipe A -
>> plane 5, cursor: 6
>> [ 48.690106] [drm:ironlake_update_wm], FIFO watermarks For pipe B -
>> plane 42, cursor: 6
>> [ 48.745204] [drm:intel_wait_for_vblank], vblank wait timed out
>> [ 48.798035] [drm:intel_wait_for_vblank], vblank wait timed out
>> [ 48.799633] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>> [ 48.802686] [drm:ironlake_fdi_link_train], FDI train 1 done.
>> [ 48.805103] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>> [ 48.807246] [drm:ironlake_fdi_link_train], FDI train 2 done.
>> [ 48.809426] [drm:ironlake_fdi_link_train], FDI train done
>> [ 48.813960] [drm:intel_update_fbc],
>> [ 48.814782] [drm:drm_crtc_helper_set_config], Setting connector
>> DPMS state to on
>> [ 48.818093] [drm:drm_crtc_helper_set_config],
>> [CONNECTOR:12:HDMI-A-2] set DPMS on
>> [ 48.828633] [drm:intel_prepare_page_flip], preparing flip with no
>> unpin work?
>> [ 49.618962] HDMI: detected monitor RX-V1800 at connection type HDMI
>> [ 49.621013] HDMI: available speakers: FL/FR LFE FC RL/RR RC RLC/RRC
>> [ 49.622304] HDMI: supports coding type LPCM: channels = 2, rates =
>> 32000 44100 48000 96000 176400 192000 384000, bits = 16 20 24
>> [ 49.625069] HDMI: supports coding type LPCM: channels = 8, rates =
>> 32000 44100 48000 96000 176400 192000 384000, bits = 16 20 24
>> [ 49.628535] HDMI: supports coding type AC-3: channels = 6, rates =
>> 32000 44100 48000, max bitrate = 640000
>> [ 49.630810] HDMI: supports coding type DTS: channels = 7, rates =
>> 32000 44100 48000 96000 176400, max bitrate = 1536000
>> [ 49.633148] HDMI: supports coding type DSD (One Bit Audio):
>> channels = 6, rates = 44100
>> [ 49.635039] HDMI: supports coding type E-AC-3/DD+ (Dolby Digital
>> Plus): channels = 8, rates = 44100 48000
>> [ 49.637130] HDMI: supports coding type MLP (Dolby TrueHD):
>> channels = 8, rates = 48000 176400 384000
>> [ 49.639172] HDMI: supports coding type DTS-HD: channels = 8, rates
>> = 48000 176400 384000
>>
>> Thanks,
>> Fengguang
> Wow, you were able to reproduce it! That's the best news ever. I will
> be applying this patch and rebuilding now to see what happens. So it
> was some sort of timing issue after all.
>
> Expect me to reply within 1h, but rebuild takes some time.
I still had the old build directory and only had to rebuild one module
which only took 5 minutes. The rest of the delay was me doing an hour of
tests as well as being on a 45 minute phone call. Anyway, now the result:
Success!
So we know it's a timing issue somewhere. Wow, real progress and near a
solution. Finally! The big question now is what causes the audio driver
to read the ELD while it is empty, and why the 1 second delay fixes it.
Look at speakertest.txt here. It's beautiful. ;-) Playing digital
multichannel sound over the HDMI PCH bus, and I can hear every channel
in their proper location on my speaker system. It's beautiful. I've
waited for this moment since building this Linux HTPC back in April. ;-)
(I'm an astonishingly patient man hehe).
Now as for why we needed a 1 second delay, any ideas? Could it be that
the audio driver was reading the ELD while it wasn't written to the
register yet?
Christopher
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HDMIB 0x0000001c sDVO/HDMI Port B Control
HDMIC 0x00000018 HDMI Port C Control
HDMID 0x80000adc HDMI Port D Control
AUD_CONFIG_A 0x00000000 Audio Configuration Transcoder A
AUD_CONFIG_B 0x00000000 Audio Configuration Transcoder B
AUD_CONFIG_C 0x00000000 Audio Configuration Transcoder C
AUD_CTS_ENABLE_A 0x00000000 Audio CTS Programming Enable Transcoder A
AUD_CTS_ENABLE_B 0x00000000 Audio CTS Programming Enable Transcoder B
AUD_CTS_ENABLE_C 0x00000000 Audio CTS Programming Enable Transcoder C
AUD_MISC_CTRL_A 0x00000044 Audio MISC Control for Transcoder A
AUD_MISC_CTRL_B 0x00000044 Audio MISC Control for Transcoder B
AUD_MISC_CTRL_C 0x00000044 Audio MISC Control for Transcoder C
AUD_VID_DID 0x80862805 Audio Vendor ID / Device ID
AUD_RID 0x00100000 Audio Revision ID
AUD_PWRST 0x00000000 Audio Power State (Function Group, Convertor, Pin Widget)
AUD_PORT_EN_HD_CFG 0x00378007 Audio Port Enable HDAudio Config
AUD_OUT_DIG_CNVT_A 0x00000000 Audio Digital Converter Conv A
AUD_OUT_DIG_CNVT_B 0x00000000 Audio Digital Converter Conv B
AUD_OUT_DIG_CNVT_C 0x00800000 Audio Digital Converter Conv C
AUD_OUT_CH_STR 0x00f7f7f7 Audio Channel ID and Stream ID
AUD_OUT_STR_DESC_A 0x00000032 Audio Stream Descriptor Format Conv A
AUD_OUT_STR_DESC_B 0x00000032 Audio Stream Descriptor Format Conv B
AUD_OUT_STR_DESC_C 0x00014011 Audio Stream Descriptor Format Conv C
AUD_PINW_CONNLNG_LIST 0x00030202 Audio Connection List
AUD_PINW_CONNLNG_SEL 0x00030202 Audio Connection Select
AUD_CNTL_ST_A 0x002354a8 Audio Control State Register Transcoder A
AUD_CNTL_ST_B 0x000054a8 Audio Control State Register Transcoder B
AUD_CNTL_ST_C 0x000054a8 Audio Control State Register Transcoder C
AUD_CNTRL_ST2 0x00000111 Audio Control State 2
AUD_CNTRL_ST3 0x00000000 Audio Control State 3
AUD_HDMIW_STATUS 0x80000000 Audio HDMI Status
AUD_HDMIW_HDMIEDID_A 0x532d5854 HDMI Data EDID Block Transcoder A
AUD_HDMIW_HDMIEDID_B 0x00000000 HDMI Data EDID Block Transcoder B
AUD_HDMIW_HDMIEDID_C 0x00000000 HDMI Data EDID Block Transcoder C
AUD_HDMIW_INFOFR_A 0x00000000 Audio Widget Data Island Packet Transcoder A
AUD_HDMIW_INFOFR_B 0x00000000 Audio Widget Data Island Packet Transcoder B
AUD_HDMIW_INFOFR_C 0x00000000 Audio Widget Data Island Packet Transcoder C
Details:
AUD_VID_DID vendor id 0x8086
AUD_VID_DID device id 0x2805
AUD_RID Major_Revision 0x1
AUD_RID Minor_Revision 0x0
AUD_RID Revision_Id 0x0
AUD_RID Stepping_Id 0x0
HDMIB Port_Enable 0
HDMIB Transcoder_Select [0x0] Transcoder A
HDMIB sDVO_Border_Enable 0
HDMIB HDCP_Port_Select 0
HDMIB Port_Detected 1
HDMIB HDMI_or_DVI_Select DVI
HDMIB Audio_Output_Enable 0
HDMIC Port_Enable 0
HDMIC Transcoder_Select [0x0] Transcoder A
HDMIC sDVO_Border_Enable 0
HDMIC HDCP_Port_Select 0
HDMIC Port_Detected 0
HDMIC HDMI_or_DVI_Select DVI
HDMIC Audio_Output_Enable 0
HDMID Port_Enable 1
HDMID Transcoder_Select [0x0] Transcoder A
HDMID sDVO_Border_Enable 1
HDMID HDCP_Port_Select 0
HDMID Port_Detected 1
HDMID HDMI_or_DVI_Select HDMI
HDMID Audio_Output_Enable 1
TRANS_DP_CTL_A DisplayPort_Enable 0
TRANS_DP_CTL_A Port_Width_Selection [0x0] x1 mode
TRANS_DP_CTL_A Port_Detected 0
TRANS_DP_CTL_A HDCP_Port_Select 0
TRANS_DP_CTL_A Audio_Output_Enable 0
TRANS_DP_CTL_B DisplayPort_Enable 0
TRANS_DP_CTL_B Port_Width_Selection [0x0] x1 mode
TRANS_DP_CTL_B Port_Detected 0
TRANS_DP_CTL_B HDCP_Port_Select 0
TRANS_DP_CTL_B Audio_Output_Enable 0
TRANS_DP_CTL_C DisplayPort_Enable 0
TRANS_DP_CTL_C Port_Width_Selection [0x0] x1 mode
TRANS_DP_CTL_C Port_Detected 0
TRANS_DP_CTL_C HDCP_Port_Select 0
TRANS_DP_CTL_C Audio_Output_Enable 0
AUD_CONFIG_A Pixel_Clock_HDMI [0x0] 25.2 / 1.001 MHz
AUD_CONFIG_B Pixel_Clock_HDMI [0x0] 25.2 / 1.001 MHz
AUD_CONFIG_C Pixel_Clock_HDMI [0x0] 25.2 / 1.001 MHz
AUD_CTS_ENABLE_A Enable_CTS_or_M_programming 0
AUD_CTS_ENABLE_A CTS_M value Index M
AUD_CTS_ENABLE_A CTS_programming 0
AUD_CTS_ENABLE_B Enable_CTS_or_M_programming 0
AUD_CTS_ENABLE_B CTS_M value Index M
AUD_CTS_ENABLE_B CTS_programming 0
AUD_CTS_ENABLE_C Enable_CTS_or_M_programming 0
AUD_CTS_ENABLE_C CTS_M value Index M
AUD_CTS_ENABLE_C CTS_programming 0
AUD_MISC_CTRL_A Sample_Fabrication_EN_bit 1
AUD_MISC_CTRL_A Sample_present_Disable 0
AUD_MISC_CTRL_A Output_Delay 4
AUD_MISC_CTRL_A Pro_Allowed 0
AUD_MISC_CTRL_B Sample_Fabrication_EN_bit 1
AUD_MISC_CTRL_B Sample_present_Disable 0
AUD_MISC_CTRL_B Output_Delay 4
AUD_MISC_CTRL_B Pro_Allowed 0
AUD_MISC_CTRL_C Sample_Fabrication_EN_bit 1
AUD_MISC_CTRL_C Sample_present_Disable 0
AUD_MISC_CTRL_C Output_Delay 4
AUD_MISC_CTRL_C Pro_Allowed 0
AUD_PWRST Func_Grp_Dev_PwrSt_Curr D0
AUD_PWRST Func_Grp_Dev_PwrSt_Set D0
AUD_PWRST ConvertorA_Widget_Power_State_Current D0
AUD_PWRST ConvertorA_Widget_Power_State_Requsted D0
AUD_PWRST ConvertorB_Widget_Power_State_Current D0
AUD_PWRST ConvertorB_Widget_Power_State_Requested D0
AUD_PWRST ConvC_Widget_PwrSt_Curr D0
AUD_PWRST ConvC_Widget_PwrSt_Req D0
AUD_PWRST PinB_Widget_Power_State_Current D0
AUD_PWRST PinB_Widget_Power_State_Set D0
AUD_PWRST PinC_Widget_Power_State_Current D0
AUD_PWRST PinC_Widget_Power_State_Set D0
AUD_PWRST PinD_Widget_Power_State_Current D0
AUD_PWRST PinD_Widget_Power_State_Set D0
AUD_PORT_EN_HD_CFG Convertor_A_Digen 1
AUD_PORT_EN_HD_CFG Convertor_B_Digen 1
AUD_PORT_EN_HD_CFG Convertor_C_Digen 1
AUD_PORT_EN_HD_CFG ConvertorA_Stream_ID 0
AUD_PORT_EN_HD_CFG ConvertorB_Stream_ID 0
AUD_PORT_EN_HD_CFG ConvertorC_Stream_ID 8
AUD_PORT_EN_HD_CFG Port_B_Out_Enable 1
AUD_PORT_EN_HD_CFG Port_C_Out_Enable 1
AUD_PORT_EN_HD_CFG Port_D_Out_Enable 1
AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status 1
AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status 1
AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status 0
AUD_OUT_DIG_CNVT_A V 0
AUD_OUT_DIG_CNVT_A VCFG 0
AUD_OUT_DIG_CNVT_A PRE 0
AUD_OUT_DIG_CNVT_A Copy 0
AUD_OUT_DIG_CNVT_A NonAudio 0x0
AUD_OUT_DIG_CNVT_A PRO 0
AUD_OUT_DIG_CNVT_A Level 0
AUD_OUT_DIG_CNVT_A Category_Code 0
AUD_OUT_DIG_CNVT_A Lowest_Channel_Number 0
AUD_OUT_DIG_CNVT_A Stream_ID 0
AUD_OUT_DIG_CNVT_B V 0
AUD_OUT_DIG_CNVT_B VCFG 0
AUD_OUT_DIG_CNVT_B PRE 0
AUD_OUT_DIG_CNVT_B Copy 0
AUD_OUT_DIG_CNVT_B NonAudio 0x0
AUD_OUT_DIG_CNVT_B PRO 0
AUD_OUT_DIG_CNVT_B Level 0
AUD_OUT_DIG_CNVT_B Category_Code 0
AUD_OUT_DIG_CNVT_B Lowest_Channel_Number 0
AUD_OUT_DIG_CNVT_B Stream_ID 0
AUD_OUT_DIG_CNVT_C V 0
AUD_OUT_DIG_CNVT_C VCFG 0
AUD_OUT_DIG_CNVT_C PRE 0
AUD_OUT_DIG_CNVT_C Copy 0
AUD_OUT_DIG_CNVT_C NonAudio 0x0
AUD_OUT_DIG_CNVT_C PRO 0
AUD_OUT_DIG_CNVT_C Level 0
AUD_OUT_DIG_CNVT_C Category_Code 0
AUD_OUT_DIG_CNVT_C Lowest_Channel_Number 0
AUD_OUT_DIG_CNVT_C Stream_ID 8
AUD_OUT_CH_STR Converter_Channel_MAP PORTB PORTC PORTD
1 1 1 1
2 2 2 2
3 16 16 16
4 16 16 16
5 16 16 16
6 16 16 16
7 16 16 16
8 16 16 16
AUD_OUT_STR_DESC_A HBR_enable 0
AUD_OUT_STR_DESC_A Convertor_Channel_Count 0
AUD_OUT_STR_DESC_A Bits_per_Sample 3
AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream 3
AUD_OUT_STR_DESC_B HBR_enable 0
AUD_OUT_STR_DESC_B Convertor_Channel_Count 0
AUD_OUT_STR_DESC_B Bits_per_Sample 3
AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream 3
AUD_OUT_STR_DESC_C HBR_enable 0
AUD_OUT_STR_DESC_C Convertor_Channel_Count 1
AUD_OUT_STR_DESC_C Bits_per_Sample 1
AUD_OUT_STR_DESC_C Number_of_Channels_in_a_Stream 2
AUD_PINW_CONNLNG_SEL Connection_select_Control_B 0
AUD_PINW_CONNLNG_SEL Connection_select_Control_C 0
AUD_PINW_CONNLNG_SEL Connection_select_Control_D 0
AUD_CNTL_ST_A DIP_Port_Select [0] Reserved
AUD_CNTL_ST_A DIP_type_enable_status Audio DIP 1
AUD_CNTL_ST_A DIP_type_enable_status Generic 1 ACP DIP 0
AUD_CNTL_ST_A DIP_type_enable_status Generic 2 DIP 0
AUD_CNTL_ST_A DIP_transmission_frequency [0x3] best effort
AUD_CNTL_ST_A ELD_ACK 0
AUD_CNTL_ST_A ELD_buffer_size 21
AUD_CNTL_ST_B DIP_Port_Select [0] Reserved
AUD_CNTL_ST_B DIP_type_enable_status Audio DIP 0
AUD_CNTL_ST_B DIP_type_enable_status Generic 1 ACP DIP 0
AUD_CNTL_ST_B DIP_type_enable_status Generic 2 DIP 0
AUD_CNTL_ST_B DIP_transmission_frequency [0x0] disabled
AUD_CNTL_ST_B ELD_ACK 0
AUD_CNTL_ST_B ELD_buffer_size 21
AUD_CNTL_ST_C DIP_Port_Select [0] Reserved
AUD_CNTL_ST_C DIP_type_enable_status Audio DIP 0
AUD_CNTL_ST_C DIP_type_enable_status Generic 1 ACP DIP 0
AUD_CNTL_ST_C DIP_type_enable_status Generic 2 DIP 0
AUD_CNTL_ST_C DIP_transmission_frequency [0x0] disabled
AUD_CNTL_ST_C ELD_ACK 0
AUD_CNTL_ST_C ELD_buffer_size 21
AUD_CNTRL_ST2 CP_ReadyB 0
AUD_CNTRL_ST2 ELD_validB 1
AUD_CNTRL_ST2 CP_ReadyC 0
AUD_CNTRL_ST2 ELD_validC 1
AUD_CNTRL_ST2 CP_ReadyD 0
AUD_CNTRL_ST2 ELD_validD 1
AUD_CNTRL_ST3 TransA_DPT_Audio_Output_En 0
AUD_CNTRL_ST3 TransA_to_Port_Sel [0] no port
AUD_CNTRL_ST3 TransB_DPT_Audio_Output_En 0
AUD_CNTRL_ST3 TransB_to_Port_Sel [0] no port
AUD_CNTRL_ST3 TransC_DPT_Audio_Output_En 0
AUD_CNTRL_ST3 TransC_to_Port_Sel [0] no port
AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Underrun 0
AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Overrun 0
AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Underrun 0
AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Overrun 0
AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Underrun 1
AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Overrun 0
AUD_HDMIW_STATUS BCLK/CDCLK_FIFO_Overrun 0
AUD_HDMIW_STATUS Function_Reset 0
AUD_HDMIW_HDMIEDID_A HDMI ELD:
10000d00 6882004f 00000000 00000000 3dcb6508
AUD_HDMIW_HDMIEDID_B HDMI ELD:
00000000 00000000 00000000 00000000 00000000
AUD_HDMIW_HDMIEDID_C HDMI ELD:
00000000 00000000 00000000 00000000 00000000
AUD_HDMIW_INFOFR_A HDMI audio Infoframe:
84010a70 01000000 00000000 00000000 00000000 00000000 00000000 00000000
AUD_HDMIW_INFOFR_B HDMI audio Infoframe:
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
AUD_HDMIW_INFOFR_C HDMI audio Infoframe:
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
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