[Intel-gfx] [PATCH] drm/i915: Hook up Ivybridge eDP

[Adam Jackson]

On Wed, 2011-11-16 at 16:29 -0800, Keith Packard wrote:
> The Ivybridge eDP control register looks like a cross between a
> Cougarpoint PCH DP control register and a Sandybridge eDP control
> register.

Your silicon people worry me.

> +/* IVB */
> +#define EDP_LINK_TRAIN_400MV_0DB_IVB		(0x24 <<22)
> +#define EDP_LINK_TRAIN_400MV_3_5DB_IVB		(0x2a <<22)
> +#define EDP_LINK_TRAIN_400MV_6DB_IVB		(0x2f <<22)
> +#define EDP_LINK_TRAIN_600MV_0DB_IVB		(0x30 <<22)
> +#define EDP_LINK_TRAIN_600MV_3_5DB_IVB		(0x36 <<22)
> +#define EDP_LINK_TRAIN_800MV_0DB_IVB		(0x38 <<22)
> +#define EDP_LINK_TRAIN_800MV_3_5DB_IVB		(0x33 <<22)
> +
> +/* legacy values */
> +#define EDP_LINK_TRAIN_500MV_0DB_IVB		(0x00 <<22)
> +#define EDP_LINK_TRAIN_1000MV_0DB_IVB		(0x20 <<22)
> +#define EDP_LINK_TRAIN_500MV_3_5DB_IVB		(0x02 <<22)
> +#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB		(0x22 <<22)
> +#define EDP_LINK_TRAIN_1000MV_6DB_IVB		(0x23 <<22)

I don't even.  Unless you're looking at some other version of the DP
spec than me, I was pretty sure those weren't legal voltage values.  And
3.5dB preemph on 1000mV gives you 1500mV at the peak, which is
definitely outside the spec.

- ajax
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