[Intel-gfx] [PATCH 8/8] drm/i915: enable rc6 by default on IVB onwards

[Daniel Vetter]

On Mon, Nov 28, 2011 at 04:15:21PM -0200, Eugeni Dodonov wrote:
> This is based on original Keith Packard's patch for enabling rc6 by
> default, with the only change that we do only enable RC6 by default on IVB
> onwards.
> 
> Due to the random issues related to RC6 on SNB when VTd is enabled, we'll
> not enable them by default on this platform yet. It can always be enabled
> by the i915.i915_enable_rc6=1 kernel parameter though.
> 
> CC: Daniel Vetter <daniel.vetter at ffwll.ch>
> CC: Ben Widawsky <ben at bwidawsk.net>
> CC: Keith Packard <keithp at keithp.com>
> CC: Jesse Barnes <jbarnes at virtuousgeek.org>
> CC: Chris Wilson <chris at chris-wilson.co.uk>
> Signed-off-by: Keith Packard <keithp at keithp.com>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c      |    4 ++--
>  drivers/gpu/drm/i915/i915_drv.h      |    2 +-
>  drivers/gpu/drm/i915/intel_display.c |   13 +++++++++++--
>  3 files changed, 14 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index a472851..9b16843 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -63,10 +63,10 @@ module_param_named(semaphores, i915_semaphores, int, 0600);
>  MODULE_PARM_DESC(semaphores,
>  		"Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
>  
> -unsigned int i915_enable_rc6 __read_mostly = 0;
> +int i915_enable_rc6 __read_mostly = 0;

Looks like the -1 default value got lost ...

>  module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
>  MODULE_PARM_DESC(i915_enable_rc6,
> -		"Enable power-saving render C-state 6 (default: true)");
> +		"Enable power-saving render C-state 6 (default: -1 (use per-chip defaults))");
>  
>  int i915_enable_fbc __read_mostly = -1;
>  module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 14e8307..e283a1d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1002,7 +1002,7 @@ extern int i915_semaphores __read_mostly;
>  extern unsigned int i915_lvds_downclock __read_mostly;
>  extern unsigned int i915_panel_use_ssc __read_mostly;
>  extern int i915_vbt_sdvo_panel_type __read_mostly;
> -extern unsigned int i915_enable_rc6 __read_mostly;
> +extern int i915_enable_rc6 __read_mostly;
>  extern int i915_enable_fbc __read_mostly;
>  extern bool i915_enable_hangcheck __read_mostly;
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 981b1f1..8d392b7 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7886,6 +7886,15 @@ void intel_init_emon(struct drm_device *dev)
>  	dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
>  }
>  
> +static bool intel_enable_rc6(struct drm_device *dev)
> +{
> +	if (i915_enable_rc6 >= 0)
> +		return i915_enable_rc6;
> +	if (INTEL_INFO(dev)->gen >= 7)
> +		return 1;
> +	return 0;
> +}
> +
>  void gen6_enable_rps(struct drm_i915_private *dev_priv)
>  {
>  	u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
> @@ -7922,7 +7931,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
>  	I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
>  	I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
>  
> -	if (i915_enable_rc6)
> +	if (intel_enable_rc6(dev_priv->dev))
>  		rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
>  			GEN6_RC_CTL_RC6_ENABLE;
>  
> @@ -8357,7 +8366,7 @@ void ironlake_enable_rc6(struct drm_device *dev)
>  	/* rc6 disabled by default due to repeated reports of hanging during
>  	 * boot and resume.
>  	 */
> -	if (!i915_enable_rc6)
> +	if (!intel_enable_rc6(dev))
>  		return;
>  
>  	mutex_lock(&dev->struct_mutex);
> -- 
> 1.7.7.4
> 

-- 
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48