[Intel-gfx] [PATCH 05/11] drm/i915: ppgtt register definitions

[Daniel Vetter]

On Tue, Nov 29, 2011 at 03:57:41PM -0800, Ben Widawsky wrote:
> On Mon, Nov 28, 2011 at 09:35:32PM +0100, Daniel Vetter wrote:
> > Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h |   18 ++++++++++++++++++
> >  1 files changed, 18 insertions(+), 0 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index e9f5dc8..7227446 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -86,6 +86,13 @@
> >  #define   GEN6_MBC_SNPCR_LOW	(2<<21)
> >  #define   GEN6_MBC_SNPCR_MIN	(3<<21) /* only 1/16th of the cache is shared */
> >  
> > +#define GEN6_MBCTL		0x0907c
> > +#define   GEN6_MBCTL_ENABLE_BOOT_FETCH	(1 << 4)
> > +#define   GEN6_MBCTL_CTX_FETCH_NEEDED	(1 << 3)
> > +#define   GEN6_MBCTL_BME_UPDATE_ENABLE	(1 << 2)
> > +#define   GEN6_MBCTL_MAE_UPDATE_ENABLE	(1 << 1)
> > +#define   GEN6_MBCTL_BOOT_FETCH_MECH	(1 << 0)
> > +
> 
> Maybe grep fail, but I don't see these registers used later in the
> series.

They're not used. But both public snb docs and Bspec contain notices that
you need to frob the boot mode enable bit in here, which afaics doesn't
exist under that exact name. Also, frobbing any of these seems to just
reduce the expected lifetime of my gpus.

But in case anyone wants to try things out, it's imo good to include the
definitions (especially since public Docs don't explain anything about
this reg than that warning about ppgtt).
-Daniel
-- 
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48