[Intel-gfx] [PATCH] drm/i915: Use PIPE_CONTROL for flushing on gen6+.

[Jesse Barnes]

On Mon, 03 Oct 2011 15:59:29 -0700
Eric Anholt <eric at anholt.net> wrote:

> On Mon, 3 Oct 2011 13:00:16 -0700, Jesse Barnes <jbarnes at virtuousgeek.org> wrote:
> > On Mon, 26 Sep 2011 11:59:23 -0700
> > Kenneth Graunke <kenneth at whitecape.org> wrote:
> > 
> > > +	/* Just flush everything for now */
> > > +	flags |= PIPE_CONTROL_WC_FLUSH;
> > > +	flags |= PIPE_CONTROL_IS_FLUSH;
> > > +	flags |= PIPE_CONTROL_TC_FLUSH;
> > > +	flags |= PIPE_CONTROL_DEPTH_FLUSH;
> > > +	flags |= PIPE_CONTROL_VFC;
> > 
> > This is the only bit I'd like to see changed.  While we still have the
> > domain tracking code we may as well try to honor it and limit our
> > flushing here like we do with MI_FLUSH.
> > 
> > Unless someone has a "remove all domain tracking" patch already posted
> > that is. :)
> 
> I don't think we "might as well try to honor it".  Working out the
> workarounds for various combinations is difficult to do even for a fixed
> set of bits.  Let's not make the workarounds more complicated by varying
> them, when experiments showed no evidence for removing bits improving
> performance.

Oh if you have experiments showing that the individual bits provide no
benefit that's fine.

-- 
Jesse Barnes, Intel Open Source Technology Center