[Intel-gfx] [PATCH 2/3] i915: Rename PIPE_CONTROL bit defines to be less terse.

[Daniel Vetter]

On Mon, Oct 03, 2011 at 11:02:39PM -0700, Kenneth Graunke wrote:
> "STALL_AT_SCOREBOARD" is much clearer than "STALL_EN" now that there are
> several different kinds of stalls.  Also, "INSTRUCTION_CACHE_FLUSH" is a
> lot easier to understand at a glance than the terse "IS_FLUSH."
> 
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
>  drivers/gpu/drm/i915/i915_reg.h         |   16 ++++++++--------
>  drivers/gpu/drm/i915/intel_ringbuffer.c |    6 ++++--
>  2 files changed, 12 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d691781..bfe8488 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -243,15 +243,15 @@
>  #define   DISPLAY_PLANE_A           (0<<20)
>  #define   DISPLAY_PLANE_B           (1<<20)
>  #define GFX_OP_PIPE_CONTROL	((0x3<<29)|(0x3<<27)|(0x2<<24))
> -#define   PIPE_CONTROL_QW_WRITE	(1<<14)
> -#define   PIPE_CONTROL_DEPTH_STALL (1<<13)
> -#define   PIPE_CONTROL_WC_FLUSH	(1<<12)
> -#define   PIPE_CONTROL_IS_FLUSH	(1<<11) /* MBZ on Ironlake */
> -#define   PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
> -#define   PIPE_CONTROL_ISP_DIS	(1<<9)
> -#define   PIPE_CONTROL_NOTIFY	(1<<8)
> +#define   PIPE_CONTROL_QW_WRITE			(1<<14)
> +#define   PIPE_CONTROL_DEPTH_STALL		(1<<13)
> +#define   PIPE_CONTROL_WRITE_FLUSH		(1<<12)
> +#define   PIPE_CONTROL_INSTRUCTION_CACHE_FLUSH	(1<<11) /* MBZ on Ironlake */
> +#define   PIPE_CONTROL_TEXTURE_CACHE_FLUSH	(1<<10) /* GM45+ only */

Minor bikeshed: You retain the _FLUSH for the read-only
instruction/texture caches, but use _INVALIDATE for the new bits for
read-only caches. I think we want _INVALIDATE for all of them.

Otherwise, these three patches are:
Reviewed-by: Daniel Vetter <daniel.vetter at ffwll.ch>

> +#define   PIPE_CONTROL_INDIRECT_STATE_DISABLE	(1<<9)
> +#define   PIPE_CONTROL_NOTIFY			(1<<8)
> +#define   PIPE_CONTROL_STALL_AT_SCOREBOARD	(1<<1)
>  #define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
> -#define   PIPE_CONTROL_STALL_EN	(1<<1) /* in addr word, Ironlake+ only */
>  
>  
>  /*
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 67ce601..2b572fd 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -468,7 +468,8 @@ pc_render_add_request(struct intel_ring_buffer *ring,
>  		return ret;
>  
>  	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | 2 | PIPE_CONTROL_QW_WRITE |
> -			PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
> +			PIPE_CONTROL_WRITE_FLUSH |
> +			PIPE_CONTROL_TEXTURE_CACHE_FLUSH);
>  	intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
>  	intel_ring_emit(ring, seqno);
>  	intel_ring_emit(ring, 0);
> @@ -484,7 +485,8 @@ pc_render_add_request(struct intel_ring_buffer *ring,
>  	scratch_addr += 128;
>  	PIPE_CONTROL_FLUSH(ring, scratch_addr);
>  	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | 2 | PIPE_CONTROL_QW_WRITE |
> -			PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
> +			PIPE_CONTROL_WRITE_FLUSH |
> +			PIPE_CONTROL_TEXTURE_CACHE_FLUSH |
>  			PIPE_CONTROL_NOTIFY);
>  	intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
>  	intel_ring_emit(ring, seqno);
> -- 
> 1.7.6.1
> 
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-- 
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48