[Intel-gfx] [PATCH 3/3] drm/i915: Force sync command ordering

[Chris Wilson]

On Tue, 11 Oct 2011 12:33:05 -0700, Ben Widawsky <ben at bwidawsk.net> wrote:
> On Tue, 11 Oct 2011 12:30:36 -0700
> Ben Widawsky <ben at bwidawsk.net> wrote:
> 
> > On Tue, 11 Oct 2011 12:18:15 -0700
> > Kenneth Graunke <kenneth at whitecape.org> wrote:
> > > 
> > > I might only enable this on Gen7 for now, unless it actually fixes
> > > something on Sandybridge.  It's not listed as required for Gen6.
> > 
> > I would prefer to keep for gen6 for two reasons:
> > 1 - paranoia
> > 2 - user space is going to be toggling a bit which it doesn't mean to
> > toggle and that has a who knows what impact on gen6.
> > 
> > Ben
> 
> I'm an idiot. Disregard this comment. Was thinking of the other hunk.
> Just 1 reason then, paranoia? Any takers?

Does PIPE_CONTROL qualify as a 3D state packet? If so without that bit
set, there is no barrier between writing to a register and attempting to
make use of it within the batch.

Sounds like justifiable paranoia to me.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre