[Intel-gfx] [PATCH 2/3] drm/i915: Rename PIPE_CONTROL bit defines to be less terse.
Ben Widawsky
ben at bwidawsk.net
Wed Oct 12 01:51:16 CEST 2011
On Tue, 11 Oct 2011 23:41:09 +0200
Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> From: Kenneth Graunke <kenneth at whitecape.org>
>
> "STALL_AT_SCOREBOARD" is much clearer than "STALL_EN" now that there are
> several different kinds of stalls. Also, "INSTRUCTION_CACHE_INVALIDATE"
> is a lot easier to understand at a glance than the terse "IS_FLUSH."
>
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> [danvet: use INVALIDATE for ro cache flags for more consistency]
> Signed-Off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++--------
> drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++++--
> 2 files changed, 12 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c4dd824..7f496a1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -243,15 +243,15 @@
> #define DISPLAY_PLANE_A (0<<20)
> #define DISPLAY_PLANE_B (1<<20)
> #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
> -#define PIPE_CONTROL_QW_WRITE (1<<14)
> -#define PIPE_CONTROL_DEPTH_STALL (1<<13)
> -#define PIPE_CONTROL_WC_FLUSH (1<<12)
> -#define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */
> -#define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
> -#define PIPE_CONTROL_ISP_DIS (1<<9)
> -#define PIPE_CONTROL_NOTIFY (1<<8)
> +#define PIPE_CONTROL_QW_WRITE (1<<14)
> +#define PIPE_CONTROL_DEPTH_STALL (1<<13)
> +#define PIPE_CONTROL_WRITE_FLUSH (1<<12)
> +#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
> +#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
> +#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
> +#define PIPE_CONTROL_NOTIFY (1<<8)
> +#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
> #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
> -#define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */
>
>
I thought we all agreed that "PIPE_CONTROL_WRITE_FLUSH" doesn't make
sense for Gen6? Or was that just me agreeing with myself?
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