[Intel-gfx] [PATCH 5/5] drm/i915: Force sync command ordering (Gen6+)
Daniel Vetter
daniel at ffwll.ch
Wed Oct 12 11:51:47 CEST 2011
On Tue, Oct 11, 2011 at 09:43:53PM -0700, Ben Widawsky wrote:
> The docs say this is required for Gen7, and since the bit was added for
> Gen6, we are also setting it there pit pf paranoia. Particularly as
> Chris points out, if PIPE_CONTROL counts as a 3d state packet.
>
> This was found through doc inspection by Ken and applies to Gen6+;
>
> It is currently hanging Daniel's maching.
No longer. The issue was utter fail in conflict resolution with the
PIPE_CONTROL patches on my side. I'm now checking whether this fixes any
of the ivb hangs I'm seeing.
-Daniel
--
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48
More information about the Intel-gfx
mailing list