[Intel-gfx] [PATCH 3/5] drm/i915/pch: Fix thinko in DPLL disable

[Jesse Barnes]

On Wed, 12 Oct 2011 15:03:11 -0700
Jesse Barnes <jbarnes at virtuousgeek.org> wrote:

> On Fri,  7 Oct 2011 14:38:44 -0400
> Adam Jackson <ajax at redhat.com> wrote:
> 
> > For transcoder A, we would never clear the DPLL[AB] select bit.  If the
> > firmware had set us up on DPLLB, the effect would be to attempt to use
> > DPLLB for both pipes A and B, which would probably be bad.
> > 
> > Signed-off-by: Adam Jackson <ajax at redhat.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c |    2 +-
> >  1 files changed, 1 insertions(+), 1 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 9edf363..67dbe22 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3051,7 +3051,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
> >  		temp = I915_READ(PCH_DPLL_SEL);
> >  		switch (pipe) {
> >  		case 0:
> > -			temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
> > +			temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
> >  			break;
> >  		case 1:
> >  			temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
> 
> I think this might be even better (goes with the 3 pipe patches)?

Ok not really better; we should still mask out the select bits just in
case the bios did something screwy.

-- 
Jesse Barnes, Intel Open Source Technology Center
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