[Intel-gfx] [PATCH] drivers: i915: Default max backlight brightness value

Simon Que sque at chromium.org
Wed Oct 26 00:52:32 CEST 2011


Hi, could I get some feedback on this patch, please?

Simon

On Fri, Oct 14, 2011 at 4:46 PM, Simon Que <sque at chromium.org> wrote:

> In the native backlight driver, use 4096 (0x1000) as the default backlight
> period, and use the period as the default max brightness.
>
> The default brightness is defined in a separate function that can be
> expanded to allow for different defaults on different systems in the
> future.
>
> Change-Id: Ie783b53dd034dcd7bf42e24ffc911cf2f10a5676
> Signed-off-by: Simon Que <sque at chromium.org>
> ---
>  drivers/gpu/drm/i915/i915_reg.h    |    1 +
>  drivers/gpu/drm/i915/intel_panel.c |   22 ++++++++++++++++++----
>  2 files changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 5d5def7..a832028 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3275,6 +3275,7 @@
>  #define  PWM_POLARITY_ACTIVE_HIGH2     (0 << 28)
>
>  #define BLC_PWM_PCH_CTL2       0xc8254
> +#define BLC_PWM_PCH_FREQ_SHIFT 16
>
>  #define PCH_PP_STATUS          0xc7200
>  #define PCH_PP_CONTROL         0xc7204
> diff --git a/drivers/gpu/drm/i915/intel_panel.c
> b/drivers/gpu/drm/i915/intel_panel.c
> index 05f500c..8205945 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -161,6 +161,12 @@ static u32 i915_read_blc_pwm_ctl(struct
> drm_i915_private *dev_priv)
>        return val;
>  }
>
> +static u32 intel_panel_get_default_backlight_period(struct drm_device
> *dev)
> +{
> +       /* The default number of clock cycles in one backlight PWM period.
> */
> +       return 0x1000;
> +}
> +
>  u32 intel_panel_get_max_backlight(struct drm_device *dev)
>  {
>        struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -168,11 +174,19 @@ u32 intel_panel_get_max_backlight(struct drm_device
> *dev)
>
>        max = i915_read_blc_pwm_ctl(dev_priv);
>        if (max == 0) {
> -               /* XXX add code here to query mode clock or hardware clock
> -                * and program max PWM appropriately.
> +               /* If no max backlight was found, use the default PWM
> period as
> +                * the max backlight value.
>                 */
> -               printk_once(KERN_WARNING "fixme: max PWM is zero.\n");
> -               return 1;
> +               max = intel_panel_get_default_backlight_period(dev);
> +               if (HAS_PCH_SPLIT(dev_priv->dev)) {
> +                       u32 val = max << BLC_PWM_PCH_FREQ_SHIFT;
> +                       I915_WRITE(BLC_PWM_PCH_CTL2, val);
> +               } else {
> +                       u32 val = max << BACKLIGHT_MODULATION_FREQ_SHIFT;
> +                       I915_WRITE(BLC_PWM_CTL, val);
> +               }
> +
> +               return max;
>        }
>
>        if (HAS_PCH_SPLIT(dev)) {
> --
> 1.7.2.3
>
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.freedesktop.org/archives/intel-gfx/attachments/20111025/e2c402aa/attachment.html>


More information about the Intel-gfx mailing list