[Intel-gfx] [PATCH] drm/i915: Use PIPE_CONTROL for flushing on gen6+.

[Chris Wilson]

On Mon, 26 Sep 2011 21:23:02 +0200, Daniel Vetter <daniel at ffwll.ch> wrote:
> On Mon, Sep 26, 2011 at 08:16:04PM +0100, Chris Wilson wrote:
> > On Mon, 26 Sep 2011 11:59:23 -0700, Kenneth Graunke <kenneth at whitecape.org> wrote:
> > > From: Jesse Barnes <jbarnes at virtuousgeek.org>
> > 
> > From the school of "If ain't broke, don't fix it" there needs to be a real
> > explanation of why this change is required here.
> > 
> > PIPE_CONTROL and its workarounds is a very bitter pill to swallow if
> > MI_FLUSH continues to function.
> 
> Lazy tlb flush, gfdt flush, seperate depth cache flush. In short, I want
> this ;-)

I feel jaded, I could have swore you just said "bug, bugs, bugs." ;-)
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre