[Intel-gfx] [PATCH] drm/i915: Use PIPE_CONTROL for flushing on gen6+.

[Kenneth Graunke]

On 09/26/2011 12:16 PM, Chris Wilson wrote:
> On Mon, 26 Sep 2011 11:59:23 -0700, Kenneth Graunke <kenneth at whitecape.org> wrote:
>> From: Jesse Barnes <jbarnes at virtuousgeek.org>
> 
> From the school of "If ain't broke, don't fix it" there needs to be a real
> explanation of why this change is required here.
> 
> PIPE_CONTROL and its workarounds is a very bitter pill to swallow if
> MI_FLUSH continues to function.
> -Chris

I hear you.

The issue is that (from Eric's reading of the simulator) MI_FLUSH seems
to be equivalent to PIPE_CONTROL with some unknown set of bits
enabled...which means we likely do need workarounds.  It's just not
clear which ones.

Also, according to the BSpec, MI_FLUSH is no longer validated or
guaranteed to work on Ivybridge.  I heard they said that about
Sandybridge as well but later recanted...I don't know if they will this
time, though.

I suspect that it actually is broke, and we do need to fix it.  This
seems like a first step.

--Kenneth