[Intel-gfx] [PATCH] Mask reserved bits in display/sprite address registers

Reese, Armin C armin.c.reese at intel.com
Mon Apr 9 17:48:03 CEST 2012

Thanks for the review, Ben.

Yes, I was a bit paranoid about what values could be in gtt_offset. But if it's always a multiple of 0x1000, we can save an additional mask operation.  I'll make the change and resubmit.


-----Original Message-----
From: Ben Widawsky [mailto:ben at bwidawsk.net] 
Sent: Friday, April 06, 2012 4:26 PM
To: Reese, Armin C
Cc: intel-gfx at lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] Mask reserved bits in display/sprite address registers

On Thu, 5 Apr 2012 20:48:20 +0000
"Reese, Armin C" <armin.c.reese at intel.com> wrote:

> The patch file for this change is attached.  Had to send it from 
> Outlook and wanted to avoid corrupting the patch. Hence, the 
> attachment.
> Armin

I don't know about the pipe stuff, but anything with gtt_offset should always be PAGE_OFFSET, and so most of the macro stuff is way overkill there. The only change is when you compare DISPSURF to gtt_offset, where it would be easier to just use PAGE_MASK.


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