[Intel-gfx] [PATCH 7/7] drm/i915: set stc evict disable lra evict w/a

[Ben Widawsky]

On Sat, Mar 31, 2012 at 11:22:03AM +0200, Daniel Vetter wrote:
> Our workaround list kindly lists that this new default value needs to
> be updated in Bspec. Naturally, this did not happen.
> 
> Signed-Off-by: Daniel Vetter <daniel.vetter at ffwll.ch>

Since the bspec says nothing, I think we need to do some performance
testing on this one. I don't even know what STC is, or how changing it's
replacement policy can impact thing.


So again, a-b because I looked at the spreadsheet, but I can't r-b this
without more info than I have at present.

> ---
>  drivers/gpu/drm/i915/i915_reg.h      |    1 +
>  drivers/gpu/drm/i915/intel_display.c |    4 ++++
>  2 files changed, 5 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5b23d5c..d0d0e2f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -576,6 +576,7 @@
>  #define   CM0_MASK_SHIFT          16
>  #define   CM0_IZ_OPT_DISABLE      (1<<6)
>  #define   CM0_ZR_OPT_DISABLE      (1<<5)
> +#define	  CM0_STC_EVICT_DISABLE_LRA_SNB	(1<<5)
>  #define   CM0_DEPTH_EVICT_DISABLE (1<<4)
>  #define   CM0_COLOR_EVICT_DISABLE (1<<3)
>  #define   CM0_DEPTH_WRITE_DISABLE (1<<1)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index dce64d8..e162d8a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8510,6 +8510,10 @@ static void gen6_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(WM2_LP_ILK, 0);
>  	I915_WRITE(WM1_LP_ILK, 0);
>  
> +	/* clear masked bit */
> +	I915_WRITE(CACHE_MODE_0,
> +		   CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT);
> +
>  	I915_WRITE(ECOSKPD, (ECO_ASYNC_FLUSH_FIX_REVERT << 16) |
>  			    ECO_ASYNC_FLUSH_FIX_REVERT);
>  
> -- 
> 1.7.7.6
> 
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