[Intel-gfx] [PATCH] drm/i915: Allow concurrent read access between CPU and GPU domain

Daniel Vetter daniel at ffwll.ch
Wed Apr 11 12:09:49 CEST 2012

On Tue, Apr 10, 2012 at 10:35:19PM +0100, Chris Wilson wrote:
> On Tue, 10 Apr 2012 11:52:50 +0100, Chris Wilson <chris at chris-wilson.co.uk> wrote:
> > Similar to allowing a buffer to be simultaneously read by the GPU and
> > through the GTT, we wish to allow readback of the pages through the CPU
> > domain whilst they are also being read by the GPU. Domain coherency
> > is managed by allowing multiple readers, but only a single writer.
> > 
> > This is used by mesa for its program cache which it may search for every
> > new program every frame and then renews should it need to add. During
> > renewal, mesa copies the program bo currently executing through a CPU
> > mapping onto the new bo. This patch allows the search and that copy to
> > proceed without causing a stall on the current batch.
> At Daniel's request, I added i-g-t/gem_cpu_concurrent_blit to catch the
> possible bugs that may have been introduced by this patch.
Queued for -next, thanks for the patch.
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48

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