[Intel-gfx] [PATCH 00/29] Haswell round 3

Eugeni Dodonov eugeni.dodonov at intel.com
Fri Apr 13 22:08:36 CEST 2012

Hi forks,

Just in time for everyone's weekend, here comes the 3rd round of patches on

As major highlights, it also adds support for HDMI/DVI outputs and multi-head
modes (I tried with VGA and HDMI).

Other than that, it is the same patches with comments from the past round
addressed (SBI locking support, proper WM calculation, better PCH items
detection, and so on).

Daniel, I think that the bits definitions, power wells, clocks programming, and
modesetting for both FDI and HDMI modes should be good to go unless someone
spots additional issues with them - so please, all of you who have something to
say about them, say it now and bikeshed as you please :).

Note that the DP and eDP modesetting support is not there yet - it will still
require a considerable amount of patches.

Also, there is one patch which fixes null pointer exceptions in gmbus code I
was having with some of the drm-intel-next-queued iterations, but I don't think
it is necessary at the moment now that gmbus stuff was disabled again (patch
5). I am not even sure if we'll hit those code paths with invalid values in
real life, so I simple added some checks for cases when we don't have a valid
adapter as it was looking too error-prone otherwise. Perhaps we could add a
WARN into them as well.

Eugeni Dodonov (29):
  drm/i915: add definition of LPT FDI port width registers
  drm/i915: add WRPLL divider programming bits
  drm/i915: add Haswell DIP controls registers
  drm/i915: support infoframes on Haswell
  drm/i915: prevent NULL pointer exception when using gmbus
  drm/i915: add support for SBI ops
  drm/i915: calculate same watermarks on Haswell as on Ivy Bridge
  drm/i915: share forcewaking code between IVB and HSW
  drm/i915: haswell has 3 pipes as well
  drm/i915: reuse Ivybridge interrupts code for Haswell
  drm/i915: share pipe count handling with Ivybridge
  drm/i915: share IVB cursor routine with Haswell
  drm/i915: show unknown sdvox registers on hdmi init
  drm/i915: do not use fdi_normal_train on haswell
  drm/i915: do not enable PCH PLL on pre-haswell
  drm/i915: detect PCH encoders on Haswell
  drm/i915: enable power wells on haswell init
  drm/i915: disable rc6 on haswell for now
  drm/i915: program WM_LINETIME on Haswell
  drm/i915: do not use old code paths on Haswell
  drm/i915: initialize DDI buffer translations
  drm/i915: perform Haswell DDI link training in FDI mode
  drm/i915: disable pipe DDI function when disabling pipe
  drm/i915: program iCLKIP on Lynx Point
  drm/i915: detect digital outputs on Haswell
  drm/i915: add support for DDI-controlled digital outputs
  drm/i915: add WR PLL programming table
  drm/i915: prepare HDMI link for Haswell
  drm/i915: hook Haswell devices in place

 drivers/char/agp/intel-agp.c         |    4 +
 drivers/gpu/drm/i915/i915_dma.c      |    2 +-
 drivers/gpu/drm/i915/i915_drv.c      |    7 +
 drivers/gpu/drm/i915/i915_irq.c      |    6 +-
 drivers/gpu/drm/i915/i915_reg.h      |   23 +
 drivers/gpu/drm/i915/intel_display.c |  763 ++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_drv.h     |    1 +
 drivers/gpu/drm/i915/intel_hdmi.c    |  602 ++++++++++++++++++++++++++-
 8 files changed, 1357 insertions(+), 51 deletions(-)


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