[Intel-gfx] [PATCH] drm/i915: enable DOP level clock gating for GEN7

[Ben Widawsky]

The docs are not very clear on exactly what this means. Another doc
however mentioned that [not] enabling this can significantly increase
consumption impact.

Some early tests show no perf regression in Nexuiz, but a fairly
significant regression in OA (252FPS -> 240FPS).

Unfortunately I do not have a good setup to check if it actually helps
with power.

CC: Daniel Vetter <daniel.vetter at ffwll.ch>
Signed-off-by: Ben Widawsky <benjamin.widawsky at intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c |    5 +++++
 drivers/gpu/drm/i915/i915_reg.h |    3 +++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 333b746..7358be8 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1218,6 +1218,11 @@ static int i915_load_gem_init(struct drm_device *dev)
 	drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
 
 	mutex_lock(&dev->struct_mutex);
+
+	if (i915_powersave && IS_IVYBRIDGE(dev))
+		I915_WRITE(GEN7_MISCCPCTL,
+			I915_READ(GEN7_MISCCPCTL) | GEN7_DOP_CLOCK_GATE_ENABLE);
+
 	if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
 		/* PPGTT pdes are stolen from global gtt ptes, so shrink the
 		 * aperture accordingly when using aliasing ppgtt. */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 972321f..db0b480 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3991,6 +3991,9 @@
 #define   GEN6_RC6			3
 #define   GEN6_RC7			4
 
+#define GEN7_MISCCPCTL			0x9424
+#define   GEN7_DOP_CLOCK_GATE_ENABLE	(1<<0)
+
 #define G4X_AUD_VID_DID			0x62020
 #define INTEL_AUDIO_DEVCL		0x808629FB
 #define INTEL_AUDIO_DEVBLC		0x80862801
-- 
1.7.10