[Intel-gfx] [PATCH] drm/i915: Don't set a MBZ bit in gen2/3 MI_FLUSH
daniel at ffwll.ch
Wed Apr 18 12:40:37 CEST 2012
On Wed, Apr 18, 2012 at 11:12:11AM +0100, Chris Wilson wrote:
> On gen2 MI_EXE_FLUSH is actually an AGP flush bit and on gen3 marked as
> reserved. On both it is documented as being must-be-zero. So obey the
> documentation, and separate the gen2 flush into its own little routine
> and share with gen3.
> This means that we can rename the existing render_ring_flush() to
> reflect the generation from which it first applies and remove the code
> for handling earlier generations from it.
> v2: Applies to gen3 as well
> v3: Make it compile and improve the commit message.
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Queued for -next, thanks for the patch.
Mail: daniel at ffwll.ch
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