[Intel-gfx] [PATCH] drm/i915: invalidate render cache on gen2

Chris Wilson chris at chris-wilson.co.uk
Thu Apr 19 16:47:44 CEST 2012

On Thu, 19 Apr 2012 16:45:22 +0200, Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> It looks like we also need to flush the render cache when we just
> invalidate it. This fixes a regression in i-g-t/gem_tiled_blits on my
> i855gm. I guess the render cache there is virtually indexed, so we
> need to clean it when changing gtt mappings.
> This regression has been introduce in
> commit 46f0f8d120c4afae53a5670bf3ac80a928340ff3
> Author: Chris Wilson <chris at chris-wilson.co.uk>
> Date:   Wed Apr 18 11:12:11 2012 +0100
>     drm/i915: Don't set a MBZ bit in gen2/3 MI_FLUSH
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Signed-Off-by: Daniel Vetter <daniel.vetter at ffwll.ch>

My fault, with hindsight comes wisdom,
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>

Chris Wilson, Intel Open Source Technology Centre

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