[Intel-gfx] [PATCH] drm/i915: Only apply the SNB pipe control w/a to gen6

[Daniel Vetter]

On Fri, Jul 20, 2012 at 06:02:28PM +0100, Chris Wilson wrote:
> The requirements for the sync flush to be emitted prior to the render
> cache flush is only true for SandyBridge. On IvyBridge and friends we
> can just emit the flushes with an inline CS stall.
> 
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

Since I've seen Ken ditch these w/a for ivb+ in mesa, I've figured that
this is ok. Some bspec reading seems to agree. Merged to dinq, thanks for
the patch.
-Daniel
-- 
Daniel Vetter
Mail: daniel at ffwll.ch
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