[Intel-gfx] [PATCH] drm/i915: Apply post-sync write for pipe control invalidates

[Daniel Vetter]

On Sat, Aug 11, 2012 at 12:20:19PM -0700, Ben Widawsky wrote:
> On Fri, 10 Aug 2012 10:18:10 +0100
> Chris Wilson <chris at chris-wilson.co.uk> wrote:
> 
> > When invalidating the TLBs it is documentated as requiring a post-sync
> > write. Failure to do so seems to result in a GPU hang.
> > 
> > Exposure to this hang on IVB seems to be a result of removing the
> > extra stalls required for SNB pipecontrol workarounds:
> > 
> > commit 6c6cf5aa9c583478b19e23149feaa92d01fb8c2d
> > Author: Chris Wilson <chris at chris-wilson.co.uk>
> > Date:   Fri Jul 20 18:02:28 2012 +0100
> > 
> >     drm/i915: Only apply the SNB pipe control w/a to gen6
> > 
> > Reported-by: yex.tian at intel.com
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=53322
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> 
> This is the moral equivalent of my patch to make the simulator happy
> on IVB. Daniel, I'll settle for either patch.
> Therefore,
> Acked-by: Ben Widawsky <ben at bwidawsk.net>

Ok, I'll wait until we have testing feedback from the bug report and then
either merge this to -fixes or -next.
-Daniel
-- 
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48