[Intel-gfx] Updated -testing branch

[Daniel Vetter]

On Sun, Aug 12, 2012 at 02:55:25PM +0200, Daniel Vetter wrote:
> Hi all,
> 
> Note that the new -next is rebased a bit and not a descendant of the old
> -nextso that I could fish out a few fixes for 3.6.
> 
> Highlights of the entire thing:
> - hsw hdmi improvements (Paulo)
> - ips/rps locking rework and cleanups
> - rc6 on ilk by default again
> - hw context&dp&dpff support for hsw (Ben)
> - GET_PARAM_HAS_SEMAPHORES (Chris)
> - gen6+ pipe_control improvements (Chris)
> - set_cacheing ioctl and assorted support code (Chris)
> - cleanups around the busy/idle/pm code (Chris&me)
> - flushing_list removal, hopefully for good (Chris)
> - read_reg ioctl (Ben)
> - support the ns2501 dvo (Thomas Richter)
> - avoid the costly gen6+ "missed IRQ" workaround where we don't need a
>   race-free seqno readback (Chris)
> - various bits&pieces, mostly early patches from the modeset rework branch
> 
> Happy testing!

Chris request a shortlog for all the new stuff in -next. Since -next is
rebased, I've included everything in the shortlog that isn't in -fixes
(i.e. all the things heading for 3.7).
-Daniel


Ben Widawsky (4):
      drm/i915: add register read IOCTL
      drm/i915: Add contexts for HSW
      drm/i915: Macro to determine DPF support
      drm/i915: Expand DPF support to Haswell

Chris Wilson (17):
      drm/i915: Cleanup context switching through do_switch()
      drm/i915: Return a mask of the active rings in the high word of busy_ioctl
      drm/i915: Allow late allocation of request for i915_add_request()
      drm/i915: Remove assertion over write domain after i915_gem_object_sync()
      drm/i915: Replace the pending_gpu_write flag with an explicit seqno
      drm/i915: Remove the defunct flushing list
      drm/i915: Remove the per-ring write list
      drm/i915: Remove explicit flush from i915_gem_object_flush_fence()
      drm/i915: Remove the explicit flush of the GPU write domain
      drm/i915: Clear the pending_gpu_fenced_access flag at the start of execbuffer
      drm/i915: Split i915_gem_flush_ring() into seperate invalidate/flush funcs
      drm/i915: Avoid concurrent access when marking the device as idle/busy
      drm/i915: Segregate memory domains in the GTT using coloring
      drm/i915: Export ability of changing cache levels to userspace
      drm/i915: Only apply the SNB pipe control w/a to gen6
      drm/i915: Add I915_GEM_PARAM_HAS_SEMAPHORES
      drm/i915: Lazily apply the SNB+ seqno w/a

Daniel Vetter (20):
      drm/i915: group ADPA #defines together
      drm/i915: simplify possible_clones computation
      drm/i915: add port parameter to intel_hdmi_init
      drm/i915: Reserve ioctl numbers for set/get_caching
      drm/i915: create VLV_DSIPLAY_BASE #define
      drm/i915: add inte_crt->adpa_reg
      drm/i915: Replace the complex flushing logic with simple invalidate/flush all
      drm/i915: Only set the down rps limit when at the loweset frequency
      drm/i915: rip out sanitize_pm again
      drm/i915: fixup desired rps frequency computation
      drm/i915: dump the device info
      drm/i915: properly guard ilk ips state
      drm/i915: fixup up debugfs rps state handling
      drm/i915: use mutex_lock_interruptible for debugfs files
      drm/i915: move all rps state into dev_priv->rps
      drm/i915: kill dev_priv->mchdev_lock
      drm/i915: DE_PCU_EVENT irq is ilk-only
      drm/i915: fix up ilk drps/ips locking
      drm/i915: enable rc6 on ilk again
      drm/i915: don't grab dev->struct_mutex for userspace forcewak

Eugeni Dodonov (1):
      drm/i915: prevent possible pin leak on error path

Paulo Zanoni (10):
      drm/i915: move common code to intel_dp_set_link_train
      drm/i915: add port field to struct intel_dp and use it
      drm/i915: fix pipe DDI mode select
      drm/i915: set the DDI sync polarity bits
      drm/i915: correctly set the DDI_FUNC_CTL bpc field
      drm/i915: completely reset the value of DDI_FUNC_CTL
      drm/i915: reindent Haswell register definitions
      drm/i915: add parentheses around PIXCLK_GATE definitions
      drm/i915: use the correct encoder type when comparing
      drm/i915: try harder to find WR PLL clock settings

Shobhit Kumar (1):
      drm/i915: Move DP structs to shared location

Thomas Richter (1):
      drm/i915: Support for ns2501-DVO
-- 
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48