[Intel-gfx] [PATCH] agp/intel, drm/i915: Use a write-combining map for updating PTEs

[Daniel Vetter]

On Sun, Aug 12, 2012 at 12:04:39PM +0100, Chris Wilson wrote:
> In order to be able to ioremap_wc the GTT space, we need to remove the
> conflicting pci_iomap from drm/i915, so we limit the register map in
> drm/i915 to the suitable range for each generation. The benefit of doing
> this is an order of magnitude reduction in time spent rewriting the GTT
> entries when inserting and removing objects. For example, this halves the
> CPU time spent in X when pushing pixels for chromium through a userptr
> (chromium has a bug where it likes to recreate its ShmPixmap on every
> draw).
> 
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

How well does this work with ums?

I guess if it blows up, we could ioremap uncached, but when kms
initializes drop that uc mapping and try to remap wc. But I fear that ums
will map the entire bar and hence we can't just unconditionally map the
gatt wc.
-Daniel
-- 
Daniel Vetter
Mail: daniel at ffwll.ch
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