[Intel-gfx] [RFC 21/30] drm/i915: enable eDP on Haswell

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni at intel.com>

Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  3 +++
 drivers/gpu/drm/i915/intel_ddi.c | 20 ++++++++++++++++++--
 drivers/gpu/drm/i915/intel_dp.c  |  2 +-
 3 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4bf4cc9..56f8617 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4399,6 +4399,9 @@
 #define  PIPE_DDI_BPC_12		(3<<20)
 #define  PIPE_DDI_PVSYNC		(1<<17)
 #define  PIPE_DDI_PHSYNC		(1<<16)
+#define  PIPE_DDI_INPUT_A_ONOFF		(4<<12)
+#define  PIPE_DDI_INPUT_B_ONOFF		(5<<12)
+#define  PIPE_DDI_INPUT_C_ONOFF		(6<<12)
 #define  PIPE_DDI_BFI_ENABLE		(1<<4)
 #define  PIPE_DDI_PORT_WIDTH_X1		(0<<1)
 #define  PIPE_DDI_PORT_WIDTH_X2		(1<<1)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ad1fb5f..44bf9e6 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -236,6 +236,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
 	case PORT_A:
 		/* We don't handle eDP and DP yet */
 		DRM_DEBUG_DRIVER("Found digital output on DDI port A\n");
+		intel_dp_init(dev, DDI_BUF_CTL_A, PORT_A);
 		break;
 	/* Assume that the  ports B, C and D are working in HDMI mode for now */
 	case PORT_B:
@@ -655,6 +656,7 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc)
 	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 		switch (intel_encoder->type) {
 		case INTEL_OUTPUT_DISPLAYPORT:
+		case INTEL_OUTPUT_EDP:
 			is_dp = true;
 			intel_dp = enc_to_intel_dp(&intel_encoder->base);
 			port = intel_dp->port;
@@ -810,7 +812,8 @@ static void intel_ddi_enable_pipe(struct intel_encoder *intel_encoder)
 		port = intel_dp->port;
 	}
 
-	I915_WRITE(PIPE_CLK_SEL(pipe), PIPE_CLK_SEL_PORT(port));
+	if (transcoder != TRANSCODER_EDP)
+		I915_WRITE(PIPE_CLK_SEL(pipe), PIPE_CLK_SEL_PORT(port));
 
 	func_val = PIPE_DDI_FUNC_ENABLE | PIPE_DDI_SELECT_PORT(port);
 	msa_val = PIPE_MSA_SYNC_CLK;
@@ -842,6 +845,18 @@ static void intel_ddi_enable_pipe(struct intel_encoder *intel_encoder)
 	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 		func_val |= PIPE_DDI_PHSYNC;
 
+	switch (pipe) {
+	case PIPE_A:
+		func_val |= PIPE_DDI_INPUT_A_ONOFF;
+		break;
+	case PIPE_B:
+		func_val |= PIPE_DDI_INPUT_B_ONOFF;
+		break;
+	case PIPE_C:
+		func_val |= PIPE_DDI_INPUT_C_ONOFF;
+		break;
+	}
+
 	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
 		if (intel_hdmi->has_hdmi_sink)
 			func_val |= PIPE_DDI_MODE_SELECT_HDMI;
@@ -997,7 +1012,8 @@ static void intel_ddi_disable_pipe(struct drm_i915_private *dev_priv,
 	temp |= PIPE_DDI_PORT_NONE;
 	I915_WRITE(DDI_FUNC_CTL(transcoder), temp);
 
-	I915_WRITE(PIPE_CLK_SEL(pipe), PIPE_CLK_SEL_DISABLED);
+	if (transcoder != TRANSCODER_EDP)
+		I915_WRITE(PIPE_CLK_SEL(pipe), PIPE_CLK_SEL_DISABLED);
 }
 
 static void intel_ddi_disable_port(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 11c7d08..afee975 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -384,7 +384,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 	 * clock divider.
 	 */
 	if (is_cpu_edp(intel_dp)) {
-		if (IS_GEN6(dev) || IS_GEN7(dev))
+		if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_HASWELL(dev))
 			aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 		else
 			aux_clock_divider = 225; /* eDP input clock at 450Mhz */
-- 
1.7.11.2