[Intel-gfx] [PATCH] drm/i915: Fix garbage pixels on top of LVDS on IVY laptop

[Takashi Iwai]

The commit [23670b322: drm/i915: CPT+ pch transcoder workaround]
caused a regression on some HP laptops with IvyBridge.  On the top of
laptop screen, a few pixels height are blinking in the whole width
constantly.  The garbage appears only on LVDS and not on other
outputs.

This patch reverts the minimum part for fixing this regression,
namely, the setup of CHICKEN2 bit in cpt_init_clock_gating().

Signed-off-by: Takashi Iwai <tiwai at suse.de>
---

Don't ask me why this fixes :)
The bug is still present in drm-intel-next-queued as of today, at
least.

Let me know if a better workaround is available.

 drivers/gpu/drm/i915/intel_pm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 58c2f21..a544029 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3446,6 +3446,9 @@ static void cpt_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
 	I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
 		   DPLS_EDP_PPS_FIX_DIS);
+	/* Without this, mode sets may fail silently on FDI */
+	for_each_pipe(pipe)
+		I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_CHICKEN2_TIMING_OVERRIDE);
 	/* WADP0ClockGatingDisable */
 	for_each_pipe(pipe) {
 		I915_WRITE(TRANS_CHICKEN1(pipe),
-- 
1.8.0.1