[Intel-gfx] [PATCH] drm/i915: The hw does not support source offsets into a YUV linear fb

[Chris Wilson]

As we can only pass in the base address of the first plane, we can not
control the offset into the subsampled chroma planes. This means that we
cannot support a source offset into a YUV* linear framebuffer. However,
for tiled framebuffers we can tell the hardware which pixels to read
from. So if we see a source offset into a linear YUV framebuffer, report
the invalid value back to userspace.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_sprite.c |   13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 97866c2..3e05d79 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -497,6 +497,19 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 			return -EINVAL;
 	}
 
+	if (obj->tiling_mode == I915_TILING_NONE && (src_x | src_y)) {
+		/* Source offsets are not supported with subsampled formats
+		 * if using a linear framebuffer.
+		 */
+		switch (fb->pixel_format) {
+		case DRM_FORMAT_YUYV:
+		case DRM_FORMAT_YVYU:
+		case DRM_FORMAT_UYVY:
+		case DRM_FORMAT_VYUY:
+			return -EINVAL;
+		}
+	}
+
 	/*
 	 * Reject any attempt to display video outside the visible area.
 	 * The caller must handle this by adjusting source offset and size.
-- 
1.7.10.4