[Intel-gfx] [PATCH] drm/i915: paper over missed irq issues with force wake vodoo
eugeni at dodonov.net
Wed Jan 4 19:15:32 CET 2012
On Wed, Jan 4, 2012 at 14:52, Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> Two things seem to do the trick on my ivb machine here:
> - prevent the gt from powering down while waiting for seqno
> notification interrupts by grabbing the force_wake in get_irq (and
> dropping it in put_irq again).
> - ordering writes from the ring's CS by reading a CS register, ACTHD
> seems to work.
> Only the blt&bsd ring on ivb seem to be massively affected by this,
> but for paranoia do this dance also on the render ring and on snb
> (i.e. all gpus with forcewake).
> Tested with Eric's glCopyPixels loop which without this patch scores a
> missed irq every few seconds.
> This patch needs my forcewake rework to use a spinlock instead of
> Cc: stable at kernel.org
> Cc: Eric Anholt <eric at anholt.net>
> Cc: Kenneth Graunke <kenneth at whitecape.org>
> Cc: Eugeni Dodonov <eugeni.dodonov at intel.com>
> Signed-Off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
This voodoo magic works here, no more missed irqs on my IVBs.
Tested-by: Eugeni Dodonov <eugeni.dodonov at intel.com>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov at intel.com>
> static u32
> +gen6_ring_get_seqno(struct intel_ring_buffer *ring)
> + /* Workaround for force correct ordering between irq and seqno
> writes on
> + * ivb (and maybe also on snb). */
> + intel_ring_get_active_head(ring);
> + return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
- the comment could be rewritten to "Workaround for force correct ordering
between irq and seqno writes on ivb (and maybe also on snb) by reading a CS
register, like ACTHD, prior reading status page".
- we could do a 'return ring_get_seqno(ring);' instead of 'return
intel_read_status_page(ring, I915_GEM_HWS_INDEX);' to reduce the Universe
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