[Intel-gfx] [PATCH] drm/i915: paper over missed irq issues with force wake vodoo

Daniel Vetter daniel at ffwll.ch
Sat Jan 14 00:52:31 CET 2012

On Fri, Jan 13, 2012 at 08:42:00AM -0800, Keith Packard wrote:
> On Wed,  4 Jan 2012 19:40:45 +0100, Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> > Two things seem to do the trick on my ivb machine here:
> > - prevent the gt from powering down while waiting for seqno
> >   notification interrupts by grabbing the force_wake in get_irq (and
> >   dropping it in put_irq again).
> > - ordering writes from the ring's CS by reading a CS register, ACTHD
> >   seems to work.
> I've rebased this code on top of drm-intel-fixes and pushed it to my
> forcewake-spinlock branch. I'd like to get this pushed to
> drm-intel-fixes in the next couple of days, get some QA coverage and
> then get it merged to master so that we can get some community testing
> early in the 3.3 cycle.

A few quick comments:
- I think we need to amend the commit msg of the voodoo patch with the
  piece of doc I've discovered. If you want I can send out a v3 with that.
- I think the HWSTAM revert is material for -next
- Can you post your 3 patches on intel-gfx, I think I can shoot at them a
  bit ;-)

acc101d drm/i915: Hold gt_lock across forcewake register reads

Imo this is a simple cleanup (reading forcewake-protected registers isn't
really a fast-path for us), so material for -next.

0f0e134 drm/i915: Hold gt_lock during reset

I still don't see what race you're trying to protect here, after all the
gpu just died, things are confusing anyway (and anyone accessing the gpu
in such a state should take that into account). Currently that's no one
afaics. So imo at most -next material.

176b987 drm/i915: Move reset forcewake processing to gen6_do_reset

Again this is imo just a cleanup. Furthermore the commit msg is lying a
bit because it fails to mention the fix to use the forcewake function
pointer. So the cleanup is imo for -next and the bugfix is really old,

> -- 
> keith.packard at intel.com

Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48

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