[Intel-gfx] [PATCH 2/2] drm/i915: Select DP BPC at mode set, rather than mode validate

Keith Packard keithp at keithp.com
Wed Jan 25 23:56:40 CET 2012

On Wed, 25 Jan 2012 23:11:00 +0100, Daniel Vetter <daniel at ffwll.ch> wrote:

> I'm a bit unhappy how generic code in intel_display.c calls function out
> of intel_dp.c. And choose_pipe_bpp_dither already has special cases for
> quite a few other encoders ... Could we add an ->adjust_bpc function to
> intel_encoder to separate this in a cleaner fashion?

Yeah, seems quite reasonable.

I can't find any reason why the lane count and link bw values are set in
fixup_mode and not just in intel_dp_set_mode. If we moved that, we could
use the bpp value computed in intel_display.c.

There's a weird mixture of code in ironlake_crtc_mode_set where it calls
intel_edp_link_config and uses those values when setting the CPU M/N
values for non-PCH eDP panels. That would also need fixing.

> I know that this isn't really the only layering violation in
> intel_display.c, but functions in that file have an uncanny ability to
> grow without bounds ;-)

The more we clean things up, the easier fixing bugs is in the future.

> As you've already said in another mail, this PCH_SPLIT here looks a bit
> strange. Could we unify these two paths here a bit?

The simple way to unify them would be to use
intel_choose_pipe_bpp_dither from the i9xx_crtc_mode_set path. Perhaps
that function could codify the currently simplistic rule used on i9xx?

keith.packard at intel.com
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