[Intel-gfx] [PATCH] drm/i915: fixup interlaced bits clearing in PIPECONF on PCH_SPLIT
przanoni at gmail.com
Sat Jan 28 16:52:12 CET 2012
2012/1/26 Daniel Vetter <daniel.vetter at ffwll.ch>:
> An identical patch has been merged for i9xx_crtc_mode_set:
> ommit 59df7b1771c150163e522f33c638096ab0efbf42
> Author: Christian Schmidt <schmidt at digadd.de>
> Date: Mon Dec 19 20:03:33 2011 +0100
> drm/intel: Fix initialization if startup happens in interlaced mode [v2]
> But that one neglected to fix up the ironlake+ path.
> This should fix the issue reported by Alfonso Fiore where booting with
> only a HDMI cable connected to his TV failed to display anything. The
> issue is that the bios set up things for 1080i and used the pannel
> fitter to scale up the lower progressive resolutions. We failed to
> clear the interlace bit in the PIPEACONF register, resulting in havoc.
> v2: Be more paranoid and just unconditionally clear the field before
> setting new values.
> Cc: Peter Ross <pross at xvid.org>
> Cc: Alfonso Fiore <alfonso.fiore at gmail.com>
> Signed-Off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
I didn't experience Alfonso's problem, but tested this patch with the
interlaced series. Tested-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
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