[Intel-gfx] [PATCH 11/43] drm/i915: Separate fence pin counting from normal bind pin counting
daniel at ffwll.ch
Sun Jan 29 17:56:33 CET 2012
On Wed, Dec 14, 2011 at 01:57:08PM +0100, Daniel Vetter wrote:
> From: Chris Wilson <chris at chris-wilson.co.uk>
> In order to correctly account for reserving space in the GTT and fences
> for a batch buffer, we need to independently track whether the fence is
> pinned due to a fenced GPU access in the batch or whether the buffer is
> pinned in the aperture. Currently we count the fenced as pinned if the
> buffer has already been seen in the execbuffer. This leads to a false
> accounting of available fence registers, causing frequent mass evictions.
> Worse, if coupled with the change to make i915_gem_object_get_fence()
> report EDADLK upon fence starvation, the batchbuffer can fail with only
> one fence required...
> Fixes intel-gpu-tools/tests/gem_fenced_exec_thrash
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38735
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Reviewed-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> Tested-by: Paul Neumann <paul104x at yahoo.de>
Queued for -next, thanks for the patch.
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48
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