[Intel-gfx] [PATCH 18/43] drm/i915: fix swizzle detection for gen3

Daniel Vetter daniel at ffwll.ch
Mon Jan 30 21:20:43 CET 2012

On Sun, Jan 29, 2012 at 05:36:04PM +0000, Chris Wilson wrote:
> On Wed, 14 Dec 2011 13:57:15 +0100, Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> > It looks like the desktop variants of i915 and i945 also have the DCC
> > register to control dram channel interleave and cpu side bit6
> > swizzling.
> > 
> > Unfortunately internal Cspec/ConfigDB documentation for these ancient chips
> > have already been dropped and there seem to be no archives. Also
> > somebody thought the swizzling behaviour is surely a worthy secret to
> > keep and redacted any mention of these fields from the published Intel
> > datasheets.
> > 
> > I suspect the hw engineers were really proud of the page coloring
> > they've achieved in their first dual channel dram controller with
> > bit17 - after all Bspec explains in great length the optimal layout of
> > page frame numbers modulo 4 for the color and depth buffers, too.
> > Later on when they've started to work on VT-d they shamefully
> > discoverd their stupidity and tried to cover the tracks ...
> > 
> > Tested-by: Daniel Vetter <daniel.vetter at ffwll.ch> (i915g)
> > Tested-by: Pavel Ondra─Źka <pavel.ondracka at email.cz> (i945g)
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=42625
> > Cc: stable at kernel.org
> > Signed-Off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> It doesn't appear to have broken any of my machines, but I'm going to
> qualify that to only the laptops I've look at the output of as well as
> having run i-g-t!
> Tested-by: Chris Wilson <chris at chris-wilson.co.uk> (no changes on 855gm, pnv, gm45, ilk, snb)
I've picked this one here up for -next. If it blows up we just need to
revert it because afaik all the documentation about this disappeared into
secret vaults.
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48

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