[Intel-gfx] [PATCH 1/2] drm/i915: flush DC writes cached in l3$ on gen7

[Eric Anholt]

Daniel Vetter <daniel.vetter at ffwll.ch> writes:

> We don't yet use this, but now that we start to look into putting that
> l3$ we better set the associated flush bit, too.
>
> Also add the only other missing PIPE_CONTROL bit #define.

Reviewed-by: Eric Anholt <eric at anholt.net>
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