[Intel-gfx] [PATCH 5/7] drm/i915: access VLV regs through read/write switch

[Daniel Vetter]

On Tue, Jun 12, 2012 at 02:47:33PM -0700, Jesse Barnes wrote:
> Since the offsets have all moved around.
> 
> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>

Oh dear, I guess we'll just life with ugly then. Just to check so that we
can still sensibly move forward with register base addresses:

Would

	if (reg >= 0x180000)
		return false;

in that function be enough to prevent this hack from adjusting display
registers that have already been adjusted for the new vlv display base
address? If so, please add that check so that we can move things to
something slightly more sensible piece-by-piece.
-Daniel



> ---
>  drivers/gpu/drm/i915/i915_drv.c |   80 ++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 78 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 238a521..747dc8d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1144,6 +1144,77 @@ MODULE_LICENSE("GPL and additional rights");
>          ((reg) != FORCEWAKE)) && \
>         (!IS_VALLEYVIEW((dev_priv)->dev))
>  
> +static bool IS_DISPLAYREG(u32 reg)
> +{
> +	if (reg >= RENDER_RING_BASE &&
> +	    reg < RENDER_RING_BASE + 0xff)
> +		return false;
> +	if (reg >= GEN6_BSD_RING_BASE &&
> +	    reg < GEN6_BSD_RING_BASE + 0xff)
> +		return false;
> +	if (reg >= BLT_RING_BASE &&
> +	    reg < BLT_RING_BASE + 0xff)
> +		return false;
> +
> +	if (reg == PGTBL_ER)
> +		return false;
> +
> +	if (reg >= IPEIR_I965 &&
> +	    reg < HWSTAM)
> +		return false;
> +
> +	if (reg == MI_MODE)
> +		return false;
> +
> +	if (reg == GFX_MODE_GEN7)
> +		return false;
> +
> +	if (reg == RENDER_HWS_PGA_GEN7 ||
> +	    reg == BSD_HWS_PGA_GEN7 ||
> +	    reg == BLT_HWS_PGA_GEN7)
> +		return false;
> +
> +	if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
> +	    reg == GEN6_BSD_RNCID)
> +		return false;
> +
> +	if (reg == GEN6_BLITTER_ECOSKPD)
> +		return false;
> +
> +	if (reg >= 0x4000c &&
> +	    reg <= 0x4002c)
> +		return false;
> +
> +	if (reg >= 0x4f000 &&
> +	    reg <= 0x4f08f)
> +		return false;
> +
> +	if (reg >= 0x4f100 &&
> +	    reg <= 0x4f11f)
> +		return false;
> +
> +	if (reg >= VLV_MASTER_IER &&
> +	    reg <= GEN6_PMIER)
> +		return false;
> +
> +	if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
> +	    reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
> +		return false;
> +
> +	if (reg >= VLV_IIR_RW &&
> +	    reg <= VLV_ISR)
> +		return false;
> +
> +	if (reg == FORCEWAKE_VLV ||
> +	    reg == FORCEWAKE_ACK_VLV)
> +		return false;
> +
> +	if (reg == GEN6_GDRST)
> +		return false;
> +
> +	return true;
> +}
> +
>  #define __i915_read(x, y) \
>  u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
>  	u##x val = 0; \
> @@ -1156,6 +1227,8 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
>  		if (dev_priv->forcewake_count == 0) \
>  			dev_priv->display.force_wake_put(dev_priv); \
>  		spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
> +	} else if (IS_DISPLAYREG(reg) && IS_VALLEYVIEW(dev_priv->dev)) { \
> +		val = read##y(dev_priv->regs + reg + 0x180000);		\
>  	} else { \
>  		val = read##y(dev_priv->regs + reg); \
>  	} \
> @@ -1175,8 +1248,11 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
>  	trace_i915_reg_rw(true, reg, val, sizeof(val)); \
>  	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
>  		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
> -	} \
> -	write##y(val, dev_priv->regs + reg); \
> +	} else if (IS_DISPLAYREG(reg) && IS_VALLEYVIEW(dev_priv->dev)) { \
> +		write##y(val, dev_priv->regs + reg + 0x180000);		\
> +	} else {							\
> +		write##y(val, dev_priv->regs + reg);			\
> +	}								\
>  	if (unlikely(__fifo_ret)) { \
>  		gen6_gt_check_fifodbg(dev_priv); \
>  	} \
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48