[Intel-gfx] [PATCH 2/7] drm/i915: Enable DP panel power sequencing for ValleyView

[Shobhit Kumar]

On 06/13/2012 01:35 PM, Daniel Vetter wrote:
> On Tue, Jun 12, 2012 at 02:47:30PM -0700, Jesse Barnes wrote:
>> From: Shobhit Kumar<shobhit.kumar at intel.com>
>>
>> VLV supports two dp panels, there are two set of panel power sequence
>> registers which needed to be programmed based on the configured
>> pipe. This patch add supports for the same
>>
>> Acked-by: Acked-by: Ben Widawsky<ben at bwidawsk.net>
>> Signed-off-by: Beeresh G<beeresh.g at intel.com>
>> Reviewed-by: Vijay Purushothaman<vijay.a.purushothaman at intel.com>
>> Reviewed-by: Jesse Barnes<jesse.barnes at intel.com>
>> Signed-off-by: Jesse Barnes<jbarnes at virtuousgeek.org>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h |   12 ++++++++++++
>>   drivers/gpu/drm/i915/intel_dp.c |    8 +++++++-
>>   2 files changed, 19 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 281446d..a9e9d92 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -3854,6 +3854,18 @@
>>
>>   #define BLC_PWM_PCH_CTL2	0xc8254
>>
>> +#define PIPEA_PP_STATUS         0x61200
>> +#define PIPEA_PP_CONTROL        0x61204
>> +#define PIPEA_PP_ON_DELAYS      0x61208
>> +#define PIPEA_PP_OFF_DELAYS     0x6120c
>> +#define PIPEA_PP_DIVISOR        0x61210
>> +
>> +#define PIPEB_PP_STATUS         0x61300
>> +#define PIPEB_PP_CONTROL        0x61304
>> +#define PIPEB_PP_ON_DELAYS      0x61308
>> +#define PIPEB_PP_OFF_DELAYS     0x6130c
>> +#define PIPEB_PP_DIVISOR        0x61310
>> +
>>   #define PCH_PP_STATUS		0xc7200
>>   #define PCH_PP_CONTROL		0xc7204
>>   #define  PANEL_UNLOCK_REGS	(0xabcd<<  16)
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 6538c46..d59af24 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -342,7 +342,13 @@ static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
>>   	struct drm_device *dev = intel_dp->base.base.dev;
>>   	struct drm_i915_private *dev_priv = dev->dev_private;
>>
>> -	return (I915_READ(PCH_PP_STATUS)&  PP_ON) != 0;
>> +	if (IS_VALLEYVIEW(dev)) {
>> +		if (I915_READ(intel_dp->output_reg)&  DP_PIPEB_SELECT)
>> +			return (I915_READ(PIPEB_PP_STATUS)&  PP_ON) != 0;
>> +		else
>> +			return (I915_READ(PIPEA_PP_STATUS)&  PP_ON) != 0;
>> +	} else
>> +		return (I915_READ(PCH_PP_STATUS)&  PP_ON) != 0;
>>   }
>>
>>   static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
>
> ... I have a feeling that this patch should be much longer ;-)
> -Daniel

Yeah :) This patch was just to just add the new registers for VLV  with 
the intention of adding incremental patches for enabling the feature. 
Somehow this did not go beyond what it is right now. Will be sending 
more patches as part of the DP/eDP enabling effort on VLV

Regards
Shobhit