[Intel-gfx] [PATCH 13/14] drm/i915: fix initial IRQ masking on VLV

[Daniel Vetter]

On Fri, Jun 15, 2012 at 11:55:25AM -0700, Jesse Barnes wrote:
> We can leave vblank interrupts masked but enabled so we're not dependent
> on the first client to toggle the disable timer.  We can also mask all
> render based interrupts, since the ring code will handle unmasking them
> for us.
> 
> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_irq.c |   12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 36732f7..5c6c5e9 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1889,7 +1889,13 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
>  		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
>  		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
>  
> -	dev_priv->irq_mask = ~enable_mask;
> +	/*
> +	 *Leave vblank interrupts masked initially.  enable/disable will
> +	 * toggle them based on usage.
> +	 */
> +	dev_priv->irq_mask = (~enable_mask) |
> +		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
> +		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
>  
>  	dev_priv->pipestat[0] = 0;
>  	dev_priv->pipestat[1] = 0;

Please squash this hunk here with the vlv pageflip patch - this little
fumble decently confused me while reviewing the patchflip patch.

> @@ -1925,11 +1931,11 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
>  		GT_SYNC_STATUS |
>  		GT_USER_INTERRUPT;
>  
> -	dev_priv->gt_irq_mask = ~render_irqs;
> +	dev_priv->gt_irq_mask = ~0;
>  
>  	I915_WRITE(GTIIR, I915_READ(GTIIR));
>  	I915_WRITE(GTIIR, I915_READ(GTIIR));
> -	I915_WRITE(GTIMR, 0);
> +	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
>  	I915_WRITE(GTIER, render_irqs);
>  	POSTING_READ(GTIER);

Presuming I haven't missed anything, render_irqs is now an unused
variable. Please also rip that out, but leave the gt_irq frobbing in a
separate patch.
-Daniel

>  
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48