[Intel-gfx] [PATCH] drm/i915: prefer wide & slow to fast & narrow in DP configs

[Jesse Barnes]

On Fri, 22 Jun 2012 10:05:19 +0100
Chris Wilson <chris at chris-wilson.co.uk> wrote:

> On Thu, 21 Jun 2012 18:13:19 -0700, Keith Packard <keithp at keithp.com> wrote:
> > Jesse Barnes <jbarnes at virtuousgeek.org> writes:
> > 
> > > High frequency link configurations have the potential to cause trouble
> > > with long and/or cheap cables, so prefer slow and wide configurations
> > > instead.  This patch has the potential to cause trouble for eDP
> > > configurations that lie about available lanes, so if we run into that we
> > > can make it conditional on eDP.
> > 
> > I *have* run into this on eDP machines already, which is why the code
> > loops this way today...
> 
> It was structured to minimise lane count because certain chipsets did
> not wire up all the lanes, right? Is that still relevant as we are using
> the advertised max_lane_count from the DPCD now?

In embedded applications, some of the lanes may not exist, but the DPCD
should indicate that (though as Keith says, some lie about it).  But if
we set aside eDP it may be safe...

-- 
Jesse Barnes, Intel Open Source Technology Center