[Intel-gfx] [PATCH 00/21] More Haswell patches

[Eugeni Dodonov]

Hi,

Those are the patches which I had in my queue for past few weeks, which I am
sending now for your bikeshedding pleasure :).

As major changes, this patch series adds support for DP, eDP and RC6
features for Haswell. Some of the DP-related patches were already posted
here, but I am resending them as part of this larger series for giving them
proper context.

Also, for DP and eDP, Paulo Zanoni and Shobhit Kumar are already working on a
larger series of patches which should appear in the next few days as well.  So
while the patches in this series should work on most configurations,
considerable amount of improvements are still to come.

(And yes, our entire intel_dp dungeon is getting too dangerous for mere
mortals to enter, so I think a refactoring of its internals is highly
needed.)

Moving to RC6, I've added the new forcewake sequence (which is mostly
similar to gen6), and a new enable/disable set of routines. Most of the
sequence is similar to what we had on SNB/IVB, but there are some changes in
registers and values. So instead of adding another layer of if(IS_HASWELL())
checks all around splitting it into a separate set of functions seems
cleaner. This also prepares the ground for additional patches which are yet
to come.

I've also added haswell_init_clock_gating routine, which is almost identical
to Ivy Bridge. The reason for this was the same as with RC6 - to avoid a
large nesting IS_HASWELL chunks on top of older code.

For both those cases, I'd be interested in your opinion on which approach
you prefer - reusing GEN6 stuff with IS_HASWELL() chunks; or splitting the
functionality into Haswell-specific routines. I can see pros and contras
with both approaches, so I am open to suggestions.

Finally, there are some small cleanup patches for LPT debug/error messages a
small fix for bogus FBC update messages, and a fix for a broken
PIPE_WM_LINETIME register from Paulo which we all overlooked somehow.

So in overall, with those patches, the status of Haswell support should be more
or less on-par with Ivy Bridge kernel-wise. Most things that were working on
IVB should be available on HSW - and if they don't work it is probably a bug,
so please let me know about it.

As usual, bikesheds, comments and suggestions are highly welcome :).

Eugeni



Eugeni Dodonov (10):
  drm/i915: re-initialize DDI buffer translations after resume
  drm/i915: simplify FDI RX check for LPT
  drm/i915: account for only one transcoder on LPT
  drm/i915: introduce lpt_enable_pch and cpt_enable_pch
  drm/i915: program FDI_RX TP and FDI delays
  drm/i915: support Haswell-style force waking
  drm/i915: add RPS configuration for Haswell
  drm/i915: introduce haswell_init_clock_gating
  drm/i915: prevent bogus intel_update_fbc notifications
  drm/i915: enable RC6 workaround on Haswell

Paulo Zanoni (1):
  drm/i915: fix PIPE_WM_LINETIME definition

Shobhit Kumar (10):
  drm/i915: Move DP structs to shared location
  drm/i915: Add support for DDI control DP outputs
  drm/i915: Add DP Helper functions for Haswell
  drm/i915: Haswell specific code for the DP Link Training
  drm/i915: Disable DDI Pipe Control on HSW while disabling pipe
  drm/i915: Hook DP init in ddi module
  drm/i915: Add EDP Registers for Haswell
  drm/i915: Timing initialization for eDP on HSW
  drm/i915: Modesetting for eDP on HSw
  drm/i915: Hook eDP initialization on DDI A

 drivers/gpu/drm/i915/i915_drv.c      |  36 +++++-
 drivers/gpu/drm/i915/i915_drv.h      |   3 +
 drivers/gpu/drm/i915/i915_reg.h      |  74 ++++++++++-
 drivers/gpu/drm/i915/intel_ddi.c     | 235 +++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_display.c | 194 ++++++++++++++++++++++-------
 drivers/gpu/drm/i915/intel_dp.c      | 171 +++++++++++++++++--------
 drivers/gpu/drm/i915/intel_drv.h     |  48 +++++++
 drivers/gpu/drm/i915/intel_pm.c      | 231 ++++++++++++++++++++++++++++++++--
 8 files changed, 878 insertions(+), 114 deletions(-)

-- 
1.7.11.1