[Intel-gfx] [PATCH 07/36] drm/i915: use the right FDI_RX_CTL register on Haswell

[Daniel Vetter]

On Wed, Oct 31, 2012 at 06:12:26PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
> 
> There is only one PCH transcoder, so it's always _FDI_RXA_CTL. Using
> "pipe" here is wrong.
> 
> While at it, also reuse the rx_ctl_val variable created in the
> previous commit.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 24 ++++++++----------------
>  1 file changed, 8 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 39a53b4..c397da3 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -153,8 +153,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	int pipe = intel_crtc->pipe;
> -	u32 reg, temp, i, rx_ctl_val;
> +	u32 temp, i, rx_ctl_val;
>  
>  	/* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
>  	 * mode set "sequence for CRT port" document:
> @@ -199,17 +198,10 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>  
>  		udelay(600);
>  
> -		/* Enable CPU FDI Receiver with auto-training */
> -		reg = FDI_RX_CTL(pipe);
> -		I915_WRITE(reg,
> -				I915_READ(reg) |
> -					FDI_LINK_TRAIN_AUTO |
> -					FDI_RX_ENABLE |
> -					FDI_LINK_TRAIN_PATTERN_1_CPT |

The LINK_TRAIN_PAT1 here seems to disappear. Is that simply because when
using auto training, we may not set this? If so, please mention that in
the commit message. All the other flags are set, safe for ...
> -					FDI_RX_ENHANCE_FRAME_ENABLE |
> -					FDI_PORT_WIDTH_2X_LPT |

... dropping the 2X_LPT mode here will blow up on low-res, see my comment
in the previous patch.
-Daniel

> -					FDI_RX_PLL_ENABLE);
> -		POSTING_READ(reg);
> +		/* Enable PCH FDI Receiver with auto-training */
> +		rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
> +		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> +		POSTING_READ(_FDI_RXA_CTL);
>  		udelay(100);
>  
>  		temp = I915_READ(DP_TP_STATUS(PORT_E));
> @@ -231,9 +223,9 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>  			I915_WRITE(DP_TP_CTL(PORT_E),
>  					I915_READ(DP_TP_CTL(PORT_E)) &
>  						~DP_TP_CTL_ENABLE);
> -			I915_WRITE(FDI_RX_CTL(pipe),
> -					I915_READ(FDI_RX_CTL(pipe)) &
> -						~FDI_RX_PLL_ENABLE);
> +
> +			rx_ctl_val &= ~FDI_RX_PLL_ENABLE;
> +			I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
>  			continue;
>  		}
>  	}
> -- 
> 1.7.11.4
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch