[Intel-gfx] [PATCH 10/36] drm/i915: program the FDI RX TUSIZE register on hsw_fdi_link_train

[Daniel Vetter]

On Wed, Oct 31, 2012 at 06:12:29PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
> 
> According to the mode set sequence documentation, this is the right
> place. According to the FDI_RX_TUSIZE register description, this is
> the value we should set.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 0cb6441..5d33f62 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -196,6 +196,9 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>  
>  		udelay(600);
>  
> +		/* Program PCH FDI Receiver TU */
> +		I915_WRITE(_FDI_RXA_TUSIZE1, 0x7E000000);
> +

I think you also want to remove the setting of RX_TU_SIZE in
lpt_pch_enable. And we have nice symbolic constants to encode that 0-based
64 shifter by 25 bits ...
-Daniel

>  		/* Enable PCH FDI Receiver with auto-training */
>  		rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
>  		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> -- 
> 1.7.11.4
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch