[Intel-gfx] [PATCH 18/36] drm/i915: don't write FDI_RX_TUSIZE on lpt_pch_enable

[Daniel Vetter]

On Wed, Oct 31, 2012 at 06:12:37PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
> 
> This is done way earlier on HSW/LPT and is just wrong here.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

Ok, I'll probably regret it right away, but I think splitting the fdi link
training code up into that many patches was a bit too much - imo it makes
reviewing more painful, since you can essentially only check things once
you have all patches applied and can look at the end result.

So in hindsight I think the following 2 patches would have been good
enough:
- move RX_TU_SIZE programming to the right spot (since that also touches
  code outside of the fdi link train code)
- fixup the fdi link train. It is essentially a complete rewrite, it's not
  a lot of code (I think just 100 lines in the end), and you pretty much
  can only check the end result with bspec. Ofc, this commit needs a nice
  big commit message that explains all the little fixes that have been
  required.

In a way this is a special case, since all the changes are concentrated
in just one fucntion and don't have any implications towards other code
outside of that function.

For other fixes that are not so well contained, I still prefer small
patches over big patches ;-)

Cheers, Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c | 5 -----
>  1 file changed, 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ee81932..f9441d1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3142,11 +3142,6 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
>  
>  	assert_transcoder_disabled(dev_priv, pipe);
>  
> -	/* Write the TU size bits before fdi link training, so that error
> -	 * detection works. */
> -	I915_WRITE(FDI_RX_TUSIZE1(pipe),
> -		   I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
> -
>  	/* XXX: pch pll's can be enabled any time before we enable the PCH
>  	 * transcoder, and we actually should do this to not upset any PCH
>  	 * transcoder that already use the clock when we share it.
> -- 
> 1.7.11.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch